The Lava.Unisim module defines the basic gates that are common to all architectures.
- inv :: Bit -> Out Bit
- and2 :: (Bit, Bit) -> Out Bit
- and3 :: (Bit, Bit, Bit) -> Out Bit
- and4 :: (Bit, Bit, Bit, Bit) -> Out Bit
- and5 :: (Bit, Bit, Bit, Bit, Bit) -> Out Bit
- and6 :: (Bit, Bit, Bit, Bit, Bit, Bit) -> Out Bit
- or2 :: (Bit, Bit) -> Out Bit
- or3 :: (Bit, Bit, Bit) -> Out Bit
- or4 :: (Bit, Bit, Bit, Bit) -> Out Bit
- or5 :: (Bit, Bit, Bit, Bit, Bit) -> Out Bit
- or6 :: (Bit, Bit, Bit, Bit, Bit, Bit) -> Out Bit
- nor2 :: (Bit, Bit) -> Out Bit
- xor2 :: (Bit, Bit) -> Out Bit
- xnor2 :: (Bit, Bit) -> Out Bit
- mux :: (Bit, (Bit, Bit)) -> Out Bit
- muxcy :: Bit -> Bit -> Bit -> Out Bit
- muxcy_d :: Bit -> Bit -> Bit -> Out (Bit, Bit)
- muxcy_l :: Bit -> Bit -> Bit -> Out (Bit, Bit)
- muxf5 :: Bit -> Bit -> Bit -> Out Bit
- muxf5_d :: Bit -> Bit -> Bit -> Out (Bit, Bit)
- muxf5_l :: Bit -> Bit -> Bit -> Out (Bit, Bit)
- muxf6 :: Bit -> Bit -> Bit -> Out Bit
- muxf6_d :: Bit -> Bit -> Bit -> Out (Bit, Bit)
- muxf6_l :: Bit -> Bit -> Bit -> Out (Bit, Bit)
- muxf7 :: Bit -> Bit -> Bit -> Out Bit
- muxf7_d :: Bit -> Bit -> Bit -> Out (Bit, Bit)
- muxf7_l :: Bit -> Bit -> Bit -> Out (Bit, Bit)
- muxf8 :: Bit -> Bit -> Bit -> Out Bit
- muxf8_d :: Bit -> Bit -> Bit -> Out (Bit, Bit)
- muxf8_l :: Bit -> Bit -> Bit -> Out (Bit, Bit)
- xorcy :: Bit -> Bit -> Out Bit
- xorcy_d :: Bit -> Bit -> Out (Bit, Bit)
- xorcy_l :: Bit -> Bit -> Out (Bit, Bit)
- fd :: Bit -> Bit -> Out Bit
- fdc :: Bit -> Bit -> Bit -> Out Bit
- fdc_1 :: Bit -> Bit -> Bit -> Out Bit
- fdce :: Bit -> Bit -> Bit -> Bit -> Out Bit
- fdce_1 :: Bit -> Bit -> Bit -> Bit -> Out Bit
- fdcp :: Bit -> Bit -> Bit -> Bit -> Out Bit
- fdcpe :: Bit -> Bit -> Bit -> Bit -> Bit -> Out Bit
- fdcpe_1 :: Bit -> Bit -> Bit -> Bit -> Bit -> Out Bit
- srl16e :: Bit -> Bit -> Bit -> Bit -> Bit -> Bit -> Bit -> Out Bit
- and2b1l :: Bit -> Bit -> Out Bit
- or2l :: Bit -> Bit -> Out Bit
- ibufg :: Bit -> Out Bit
- bufg :: Bit -> Out Bit
- bufgp :: Bit -> Out Bit
- obufg :: Bit -> Out Bit
- obufds :: Bit -> Out (Bit, Bit)
Lava Gates
LUT-based gates
The inv
function implements an invertor explicitly with a LUT1.
The and2
function implements an AND gate explicitly with a LUT2.
The and3
function implements an AND gate explicitly with a LUT3.
The and4
function implements an AND gate explicitly with a LUT4.
The and5
function implements an AND gate explicitly with a LUT5.
The and6
function implements an AND gate explicitly with a LUT6.
The or2
function implements an OR gate explicitly with a LUT2.
The or3
function implements an AND gate explicitly with a LUT3.
The or4
function implements an AND gate explicitly with a LUT4.
The or5
function implements an AND gate explicitly with a LUT5.
The and6
function implements an AND gate explicitly with a LUT6.
The nor2
function implements an NOR gate explicitly with a LUT2.
The xor2
function implements an XOR gate explicitly with a LUT2.
The xnor2
function implements an XOR gate explicitly with a LUT2.
A multiplexor implemented with a LUT3
Carry-chain elements
Flip-flops
Shift-register primitives
16-bit shift register look-up table with clock enable
Gates implemented in place of a slice latch
Two input and gate implemented in place of a slice latch