clash-prelude-0.11.1: CAES Language for Synchronous Hardware - Prelude library

Copyright (C) 2013-2016 University of Twente BSD2 (see the file LICENSE) Christiaan Baaij Unsafe Haskell2010 ScopedTypeVariablesExplicitForAll

CLaSH.Prelude.Testbench

Description

Synopsis

# Testbench functions for circuits synchronised to the system slock

Arguments

 :: (Eq a, Show a) => String Additional message -> Signal a Checked value -> Signal a Expected value -> Signal b Return value -> Signal b

Compares the first two Signals for equality and logs a warning when they are not equal. The second Signal is considered the expected value. This function simply returns the third Signal unaltered as its result. This function is used by outputVerifier.

NB: This function can be used in synthesizable designs.

Arguments

 :: KnownNat l => Vec l a Samples to generate -> Signal a Signal of given samples

To be used as one of the functions to create the "magical" testInput value, which the CλaSH compiler looks for to create the stimulus generator for the generated VHDL testbench.

Example:

testInput :: Signal Int
testInput = stimuliGenerator $(listToVecTH [(1::Int),3..21])  >>> sampleN 13 testInput [1,3,5,7,9,11,13,15,17,19,21,21,21]  Arguments  :: (KnownNat l, Eq a, Show a) => Vec l a Samples to compare with -> Signal a Signal to verify -> Signal Bool Indicator that all samples are verified To be used as one of the functions to generate the "magical" expectedOutput function, which the CλaSH compiler looks for to create the signal verifier for the generated VHDL testbench. Example: expectedOutput :: Signal Int -> Signal Bool expectedOutput = outputVerifier$(listToVecTH ([70,99,2,3,4,5,7,8,9,10]::[Int]))

>>> import qualified Data.List as List
>>> sampleN 12 (expectedOutput (fromList ([0..10] List.++ [10,10,10])))

cycle(system1000): 0, outputVerifier
expected value: 70, not equal to actual value: 0
[False
cycle(system1000): 1, outputVerifier
expected value: 99, not equal to actual value: 1
,False,False,False,False,False
cycle(system1000): 6, outputVerifier
expected value: 7, not equal to actual value: 6
,False
cycle(system1000): 7, outputVerifier
expected value: 8, not equal to actual value: 7
,False
cycle(system1000): 8, outputVerifier
expected value: 9, not equal to actual value: 8
,False
cycle(system1000): 9, outputVerifier
expected value: 10, not equal to actual value: 9
,False,True,True]


# Testbench functions for circuits synchronised to arbitrary clocks

Arguments

 :: (Eq a, Show a) => SClock t -> String Additional message -> Signal' t a Checked value -> Signal' t a Expected value -> Signal' t b Return value -> Signal' t b

Compares the first two Signal's for equality and logs a warning when they are not equal. The second Signal' is considered the expected value. This function simply returns the third Signal' unaltered as its result. This function is used by outputVerifier'.

NB: This function can be used in synthesizable designs.

Arguments

 :: KnownNat l => SClock clk Clock to which to synchronize the output signal -> Vec l a Samples to generate -> Signal' clk a Signal of given samples

To be used as one of the functions to create the "magical" testInput value, which the CλaSH compiler looks for to create the stimulus generator for the generated VHDL testbench.

Example:

type ClkA = Clk "A" 100

clkA :: SClock ClkA
clkA = sclock

testInput' :: Signal' clkA Int
testInput' = stimuliGenerator' clkA $(listToVecTH [(1::Int),3..21])  >>> sampleN 13 testInput' [1,3,5,7,9,11,13,15,17,19,21,21,21]  Arguments  :: (KnownNat l, Eq a, Show a) => SClock clk Clock to which the input signal is synchronized to -> Vec l a Samples to compare with -> Signal' clk a Signal to verify -> Signal' clk Bool Indicator that all samples are verified To be used as one of the functions to generate the "magical" expectedOutput function, which the CλaSH compiler looks for to create the signal verifier for the generated VHDL testbench. Example: type ClkA = Clk "A" 100 clkA :: SClock ClkA clkA = sclock expectedOutput' :: Signal' ClkA Int -> Signal' ClkA Bool expectedOutput' = outputVerifier' clkA$(listToVecTH ([70,99,2,3,4,5,7,8,9,10]::[Int]))

>>> import qualified Data.List as List
>>> sampleN 12 (expectedOutput' (fromList ([0..10] List.++ [10,10,10])))

cycle(A100): 0, outputVerifier
expected value: 70, not equal to actual value: 0
[False
cycle(A100): 1, outputVerifier
expected value: 99, not equal to actual value: 1
,False,False,False,False,False
cycle(A100): 6, outputVerifier
expected value: 7, not equal to actual value: 6
,False
cycle(A100): 7, outputVerifier
expected value: 8, not equal to actual value: 7
,False
cycle(A100): 8, outputVerifier
expected value: 9, not equal to actual value: 8
,False
cycle(A100): 9, outputVerifier
expected value: 10, not equal to actual value: 9
,False,True,True]