clash-systemverilog-0.6.6: CAES Language for Synchronous Hardware - SystemVerilog backend

Copyright(C) 2015-2016, University of Twente
LicenseBSD2 (see the file LICENSE)
MaintainerChristiaan Baaij <christiaan.baaij@gmail.com>
Safe HaskellNone
LanguageHaskell2010

CLaSH.Backend.SystemVerilog

Description

Generate SystemVerilog for assorted Netlist datatypes

Synopsis

Documentation

data SystemVerilogState Source

State for the SystemVerilogM monad: