clash-verilog-0.6.7: CAES Language for Synchronous Hardware - Verilog backend

Copyright(C) 2015-2016, University of Twente
LicenseBSD2 (see the file LICENSE)
MaintainerChristiaan Baaij <christiaan.baaij@gmail.com>
Safe HaskellNone
LanguageHaskell2010

CLaSH.Backend.Verilog

Description

Generate Verilog for assorted Netlist datatypes

Synopsis

Documentation

data VerilogState Source

State for the VerilogM monad:

Instances