Copyright | (c) ES Group, KTH/ICT/ES 2007-2013 |
---|---|
License | BSD-style (see the file LICENSE) |
Maintainer | forsyde-dev@ict.kth.se |
Stability | experimental |
Portability | portable |
Safe Haskell | None |
Language | Haskell98 |
This module provides the VHDL backend of ForSyDe's embedded compiler
- writeVHDL :: SysDef a -> IO ()
- writeVHDLOps :: VHDLOps -> SysDef a -> IO ()
- writeAndModelsimVHDL :: SysFunToIOSimFun sysF simF => Maybe Int -> SysDef sysF -> simF
- writeAndModelsimVHDLOps :: SysFunToIOSimFun sysF simF => VHDLOps -> Maybe Int -> SysDef sysF -> simF
- writeAndGhdlVHDL :: SysFunToIOSimFun sysF simF => Maybe Int -> SysDef sysF -> simF
- writeAndGhdlVHDLOps :: SysFunToIOSimFun sysF simF => VHDLOps -> Maybe Int -> SysDef sysF -> simF
- data VHDLOps = VHDLOps {}
- data QuartusOps = QuartusOps {}
- data QuartusAction
- checkSynthesisQuartus :: QuartusOps
- data VHDLDebugLevel
- data VHDLRecursivity
- defaultVHDLOps :: VHDLOps
Documentation
writeVHDL :: SysDef a -> IO () Source #
Given a System Definition whose name is a valid VHDL _basic_ identifier
(call it "A") generate A.vhd
in current working directory using
default compilation options.
Imp: the input and output signal names of A must be valid VHDL identifiers
(basic or extended) and different to clk
and reset
which are reserved for the main clock and reset signals
writeVHDLOps :: VHDLOps -> SysDef a -> IO () Source #
writeVHDL
-alternative which allows setting VHDL compilation options.
:: SysFunToIOSimFun sysF simF | |
=> Maybe Int | Number of cycles to simulate
if |
-> SysDef sysF | system definition to simulate |
-> simF |
Generate a function which, given a system definition and some simulation stimuli:
- Writes a VHDL model of the system
- Simulates the VHDL model with Modelsim getting the results back to Haskell
writeAndModelsimVHDLOps :: SysFunToIOSimFun sysF simF => VHDLOps -> Maybe Int -> SysDef sysF -> simF Source #
VHDLOps
-alternative of writeAndModelsimVHDL
, note that
compileModelSim will implicitly be set to True
:: SysFunToIOSimFun sysF simF | |
=> Maybe Int | Number of cycles to simulate
if |
-> SysDef sysF | system definition to simulate |
-> simF |
Generate a function which, given a system definition and some simulation stimuli:
- Writes a VHDL model of the system
- Simulates the VHDL model with Ghdl getting the results back to Haskell
writeAndGhdlVHDLOps :: SysFunToIOSimFun sysF simF => VHDLOps -> Maybe Int -> SysDef sysF -> simF Source #
VHDLOps
-alternative of writeAndGhdlVHDL
VHDL Compilation options
VHDLOps | |
|
data QuartusOps Source #
Options passed to Quartus II by the VHDL Backend. Most of them are optional and Quartus will use a default value.
It contains:
- What action to perform
- Optinally, the minimum acceptable clock frequency (fMax) expressed in MHz
- FPGA family and specific device model (both are independently optional).
- Pin assignments, in the form (VHDL Pin, FPGA Pin). Note that Quartus will automatically split composite VHDL ports
data QuartusAction Source #
Action to perform by Quartus
AnalysisAndElaboration | Analysis and eleboration flow |
AnalysisAndSynthesis | Call map executable |
FullCompilation | Compile flow |
checkSynthesisQuartus :: QuartusOps Source #
Options to check if the model is synthesizable, all options except the action to take are set to default.
data VHDLDebugLevel Source #
Debug level
data VHDLRecursivity Source #
Recursivity, should the parent systems of system instances be compiled as well?
defaultVHDLOps :: VHDLOps Source #
Default traversing options