module Ice40.GB where
import Clash.Prelude
import Clash.Annotations.Primitive
import Data.String.Interpolate (i)
import Data.String.Interpolate.Util (unindent)
{-# ANN gbPrim (InlinePrimitive [Verilog] $ unindent [i|
[ { "BlackBox" :
{ "name" : "Ice40.GB.gbPrim"
, "kind" : "Declaration"
, "type" :
"gbPrim
:: Clock dom -- ARG[0]
-> Clock dom"
, "template" :
"//SB_GB begin
SB_GB ~GENSYM[sb_gb_inst][0] (
.USER_SIGNAL_TO_GLOBAL_BUFFER ( ~ARG[0] ),
.GLOBAL_BUFFER_OUTPUT ( ~RESULT )
);
//SB_GB end"
}
}
]
|]) #-}
{-# NOINLINE gbPrim #-}
gbPrim :: Clock dom -> Clock dom
gbPrim :: Clock dom -> Clock dom
gbPrim !Clock dom
clk = Clock dom
clk