module Ice40.Mac
( mac
, Input(..)
, defaultInput
, Parameter(..)
, defaultParameter
) where
import Clash.Prelude
import Ice40.Mac.Prim
data Input dom = Input
{ Input dom -> Signal dom Bit
ce :: Signal dom Bit
, Input dom -> Signal dom (BitVector 16)
c :: Signal dom (BitVector 16)
, Input dom -> Signal dom (BitVector 16)
a :: Signal dom (BitVector 16)
, Input dom -> Signal dom (BitVector 16)
b :: Signal dom (BitVector 16)
, Input dom -> Signal dom (BitVector 16)
d :: Signal dom (BitVector 16)
, Input dom -> Signal dom Bit
irsttop :: Signal dom Bit
, Input dom -> Signal dom Bit
irstbot :: Signal dom Bit
, Input dom -> Signal dom Bit
orsttop :: Signal dom Bit
, Input dom -> Signal dom Bit
orstbot :: Signal dom Bit
, Input dom -> Signal dom Bit
ahold :: Signal dom Bit
, Input dom -> Signal dom Bit
bhold :: Signal dom Bit
, Input dom -> Signal dom Bit
chold :: Signal dom Bit
, Input dom -> Signal dom Bit
dhold :: Signal dom Bit
, Input dom -> Signal dom Bit
oholdtop :: Signal dom Bit
, Input dom -> Signal dom Bit
oholdbot :: Signal dom Bit
, Input dom -> Signal dom Bit
addsubtop :: Signal dom Bit
, Input dom -> Signal dom Bit
addsubbot :: Signal dom Bit
, Input dom -> Signal dom Bit
oloadtop :: Signal dom Bit
, Input dom -> Signal dom Bit
oloadbot :: Signal dom Bit
, Input dom -> Signal dom Bit
accumci :: Signal dom Bit
, Input dom -> Signal dom Bit
signextin :: Signal dom Bit
, Input dom -> Signal dom Bit
ci :: Signal dom Bit
}
defaultInput :: Input dom
defaultInput :: Input dom
defaultInput = Input :: forall (dom :: Domain).
Signal dom Bit
-> Signal dom (BitVector 16)
-> Signal dom (BitVector 16)
-> Signal dom (BitVector 16)
-> Signal dom (BitVector 16)
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Input dom
Input
{ ce :: Signal dom Bit
ce = Signal dom Bit
1
, c :: Signal dom (BitVector 16)
c = Signal dom (BitVector 16)
0
, a :: Signal dom (BitVector 16)
a = Signal dom (BitVector 16)
0
, b :: Signal dom (BitVector 16)
b = Signal dom (BitVector 16)
0
, d :: Signal dom (BitVector 16)
d = Signal dom (BitVector 16)
0
, irsttop :: Signal dom Bit
irsttop = Signal dom Bit
0
, irstbot :: Signal dom Bit
irstbot = Signal dom Bit
0
, orsttop :: Signal dom Bit
orsttop = Signal dom Bit
0
, orstbot :: Signal dom Bit
orstbot = Signal dom Bit
0
, ahold :: Signal dom Bit
ahold = Signal dom Bit
0
, bhold :: Signal dom Bit
bhold = Signal dom Bit
0
, chold :: Signal dom Bit
chold = Signal dom Bit
0
, dhold :: Signal dom Bit
dhold = Signal dom Bit
0
, oholdtop :: Signal dom Bit
oholdtop = Signal dom Bit
0
, oholdbot :: Signal dom Bit
oholdbot = Signal dom Bit
0
, addsubtop :: Signal dom Bit
addsubtop = Signal dom Bit
0
, addsubbot :: Signal dom Bit
addsubbot = Signal dom Bit
0
, oloadtop :: Signal dom Bit
oloadtop = Signal dom Bit
0
, oloadbot :: Signal dom Bit
oloadbot = Signal dom Bit
0
, accumci :: Signal dom Bit
accumci = Signal dom Bit
0
, signextin :: Signal dom Bit
signextin = Signal dom Bit
0
, ci :: Signal dom Bit
ci = Signal dom Bit
0
}
data Parameter = Parameter
{ Parameter -> Bit
negTrigger :: Bit
, Parameter -> Bit
aReg :: Bit
, Parameter -> Bit
bReg :: Bit
, Parameter -> Bit
cReg :: Bit
, Parameter -> Bit
dReg :: Bit
, Parameter -> Bit
top8x8MultReg :: Bit
, Parameter -> Bit
bot8x8MultReg :: Bit
, Parameter -> Bit
pipeline16x16MultReg1 :: Bit
, Parameter -> Bit
pipeline16x16MultReg2 :: Bit
, Parameter -> BitVector 2
topOutputSelect :: BitVector 2
, Parameter -> BitVector 2
topAddSubLowerInput :: BitVector 2
, Parameter -> Bit
topAddSubUpperInput :: Bit
, Parameter -> BitVector 2
topAddSubCarrySelect :: BitVector 2
, Parameter -> BitVector 2
botOutputSelect :: BitVector 2
, Parameter -> BitVector 2
botAddSubLowerInput :: BitVector 2
, Parameter -> Bit
botAddSubUpperInput :: Bit
, Parameter -> BitVector 2
botAddSubCarrySelect :: BitVector 2
, Parameter -> Bit
mode8x8 :: Bit
, Parameter -> Bit
aSigned :: Bit
, Parameter -> Bit
bSigned :: Bit
}
defaultParameter :: Parameter
defaultParameter :: Parameter
defaultParameter = Parameter :: Bit
-> Bit
-> Bit
-> Bit
-> Bit
-> Bit
-> Bit
-> Bit
-> Bit
-> BitVector 2
-> BitVector 2
-> Bit
-> BitVector 2
-> BitVector 2
-> BitVector 2
-> Bit
-> BitVector 2
-> Bit
-> Bit
-> Bit
-> Parameter
Parameter
{ negTrigger :: Bit
negTrigger = Bit
0
, aReg :: Bit
aReg = Bit
0
, bReg :: Bit
bReg = Bit
0
, cReg :: Bit
cReg = Bit
0
, dReg :: Bit
dReg = Bit
0
, top8x8MultReg :: Bit
top8x8MultReg = Bit
0
, bot8x8MultReg :: Bit
bot8x8MultReg = Bit
0
, pipeline16x16MultReg1 :: Bit
pipeline16x16MultReg1 = Bit
0
, pipeline16x16MultReg2 :: Bit
pipeline16x16MultReg2 = Bit
0
, topOutputSelect :: BitVector 2
topOutputSelect = BitVector 2
0
, topAddSubLowerInput :: BitVector 2
topAddSubLowerInput = BitVector 2
0
, topAddSubUpperInput :: Bit
topAddSubUpperInput = Bit
0
, topAddSubCarrySelect :: BitVector 2
topAddSubCarrySelect = BitVector 2
0
, botOutputSelect :: BitVector 2
botOutputSelect = BitVector 2
0
, botAddSubLowerInput :: BitVector 2
botAddSubLowerInput = BitVector 2
0
, botAddSubUpperInput :: Bit
botAddSubUpperInput = Bit
0
, botAddSubCarrySelect :: BitVector 2
botAddSubCarrySelect = BitVector 2
0
, mode8x8 :: Bit
mode8x8 = Bit
0
, aSigned :: Bit
aSigned = Bit
0
, bSigned :: Bit
bSigned = Bit
0
}
mac
:: HiddenClock dom
=> Parameter
-> Input dom
-> ( Signal dom (BitVector 32)
, Signal dom Bit
, Signal dom Bit
, Signal dom Bit
)
mac :: Parameter
-> Input dom
-> (Signal dom (BitVector 32), Signal dom Bit, Signal dom Bit,
Signal dom Bit)
mac Parameter{BitVector 2
Bit
bSigned :: Bit
aSigned :: Bit
mode8x8 :: Bit
botAddSubCarrySelect :: BitVector 2
botAddSubUpperInput :: Bit
botAddSubLowerInput :: BitVector 2
botOutputSelect :: BitVector 2
topAddSubCarrySelect :: BitVector 2
topAddSubUpperInput :: Bit
topAddSubLowerInput :: BitVector 2
topOutputSelect :: BitVector 2
pipeline16x16MultReg2 :: Bit
pipeline16x16MultReg1 :: Bit
bot8x8MultReg :: Bit
top8x8MultReg :: Bit
dReg :: Bit
cReg :: Bit
bReg :: Bit
aReg :: Bit
negTrigger :: Bit
bSigned :: Parameter -> Bit
aSigned :: Parameter -> Bit
mode8x8 :: Parameter -> Bit
botAddSubCarrySelect :: Parameter -> BitVector 2
botAddSubUpperInput :: Parameter -> Bit
botAddSubLowerInput :: Parameter -> BitVector 2
botOutputSelect :: Parameter -> BitVector 2
topAddSubCarrySelect :: Parameter -> BitVector 2
topAddSubUpperInput :: Parameter -> Bit
topAddSubLowerInput :: Parameter -> BitVector 2
topOutputSelect :: Parameter -> BitVector 2
pipeline16x16MultReg2 :: Parameter -> Bit
pipeline16x16MultReg1 :: Parameter -> Bit
bot8x8MultReg :: Parameter -> Bit
top8x8MultReg :: Parameter -> Bit
dReg :: Parameter -> Bit
cReg :: Parameter -> Bit
bReg :: Parameter -> Bit
aReg :: Parameter -> Bit
negTrigger :: Parameter -> Bit
..} Input{Signal dom (BitVector 16)
Signal dom Bit
ci :: Signal dom Bit
signextin :: Signal dom Bit
accumci :: Signal dom Bit
oloadbot :: Signal dom Bit
oloadtop :: Signal dom Bit
addsubbot :: Signal dom Bit
addsubtop :: Signal dom Bit
oholdbot :: Signal dom Bit
oholdtop :: Signal dom Bit
dhold :: Signal dom Bit
chold :: Signal dom Bit
bhold :: Signal dom Bit
ahold :: Signal dom Bit
orstbot :: Signal dom Bit
orsttop :: Signal dom Bit
irstbot :: Signal dom Bit
irsttop :: Signal dom Bit
d :: Signal dom (BitVector 16)
b :: Signal dom (BitVector 16)
a :: Signal dom (BitVector 16)
c :: Signal dom (BitVector 16)
ce :: Signal dom Bit
ci :: forall (dom :: Domain). Input dom -> Signal dom Bit
signextin :: forall (dom :: Domain). Input dom -> Signal dom Bit
accumci :: forall (dom :: Domain). Input dom -> Signal dom Bit
oloadbot :: forall (dom :: Domain). Input dom -> Signal dom Bit
oloadtop :: forall (dom :: Domain). Input dom -> Signal dom Bit
addsubbot :: forall (dom :: Domain). Input dom -> Signal dom Bit
addsubtop :: forall (dom :: Domain). Input dom -> Signal dom Bit
oholdbot :: forall (dom :: Domain). Input dom -> Signal dom Bit
oholdtop :: forall (dom :: Domain). Input dom -> Signal dom Bit
dhold :: forall (dom :: Domain). Input dom -> Signal dom Bit
chold :: forall (dom :: Domain). Input dom -> Signal dom Bit
bhold :: forall (dom :: Domain). Input dom -> Signal dom Bit
ahold :: forall (dom :: Domain). Input dom -> Signal dom Bit
orstbot :: forall (dom :: Domain). Input dom -> Signal dom Bit
orsttop :: forall (dom :: Domain). Input dom -> Signal dom Bit
irstbot :: forall (dom :: Domain). Input dom -> Signal dom Bit
irsttop :: forall (dom :: Domain). Input dom -> Signal dom Bit
d :: forall (dom :: Domain). Input dom -> Signal dom (BitVector 16)
b :: forall (dom :: Domain). Input dom -> Signal dom (BitVector 16)
a :: forall (dom :: Domain). Input dom -> Signal dom (BitVector 16)
c :: forall (dom :: Domain). Input dom -> Signal dom (BitVector 16)
ce :: forall (dom :: Domain). Input dom -> Signal dom Bit
..}
= Bit
-> Bit
-> Bit
-> Bit
-> Bit
-> Bit
-> Bit
-> Bit
-> Bit
-> BitVector 2
-> BitVector 2
-> Bit
-> BitVector 2
-> BitVector 2
-> BitVector 2
-> Bit
-> BitVector 2
-> Bit
-> Bit
-> Bit
-> Clock dom
-> Signal dom Bit
-> Signal dom (BitVector 16)
-> Signal dom (BitVector 16)
-> Signal dom (BitVector 16)
-> Signal dom (BitVector 16)
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> (Signal dom (BitVector 32), Signal dom Bit, Signal dom Bit,
Signal dom Bit)
forall (dom :: Domain).
Bit
-> Bit
-> Bit
-> Bit
-> Bit
-> Bit
-> Bit
-> Bit
-> Bit
-> BitVector 2
-> BitVector 2
-> Bit
-> BitVector 2
-> BitVector 2
-> BitVector 2
-> Bit
-> BitVector 2
-> Bit
-> Bit
-> Bit
-> Clock dom
-> Signal dom Bit
-> Signal dom (BitVector 16)
-> Signal dom (BitVector 16)
-> Signal dom (BitVector 16)
-> Signal dom (BitVector 16)
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> Signal dom Bit
-> (Signal dom (BitVector 32), Signal dom Bit, Signal dom Bit,
Signal dom Bit)
macPrim Bit
negTrigger
Bit
aReg
Bit
bReg
Bit
cReg
Bit
dReg
Bit
top8x8MultReg
Bit
bot8x8MultReg
Bit
pipeline16x16MultReg1
Bit
pipeline16x16MultReg2
BitVector 2
topOutputSelect
BitVector 2
topAddSubLowerInput
Bit
topAddSubUpperInput
BitVector 2
topAddSubCarrySelect
BitVector 2
botOutputSelect
BitVector 2
botAddSubLowerInput
Bit
botAddSubUpperInput
BitVector 2
botAddSubCarrySelect
Bit
mode8x8
Bit
aSigned
Bit
bSigned
Clock dom
forall (dom :: Domain). HiddenClock dom => Clock dom
hasClock
Signal dom Bit
ce
Signal dom (BitVector 16)
c
Signal dom (BitVector 16)
a
Signal dom (BitVector 16)
b
Signal dom (BitVector 16)
d
Signal dom Bit
irsttop
Signal dom Bit
irstbot
Signal dom Bit
orsttop
Signal dom Bit
orstbot
Signal dom Bit
ahold
Signal dom Bit
bhold
Signal dom Bit
chold
Signal dom Bit
dhold
Signal dom Bit
oholdtop
Signal dom Bit
oholdbot
Signal dom Bit
addsubtop
Signal dom Bit
addsubbot
Signal dom Bit
oloadtop
Signal dom Bit
oloadbot
Signal dom Bit
accumci
Signal dom Bit
signextin
Signal dom Bit
ci