RetroClash.Delayed

Documentation

delayVGA :: (KnownNat d, KnownNat r, KnownNat g, KnownNat b) => HiddenClockResetEnable dom => VGASync dom -> DSignal dom d (Unsigned r, Unsigned g, Unsigned b) -> VGAOut dom r g b

delayedRom :: HiddenClockResetEnable dom => (forall dom'. HiddenClockResetEnable dom' => Signal dom' addr -> Signal dom' a) -> DSignal dom d addr -> DSignal dom (d + 1) a

delayedRam :: HiddenClockResetEnable dom => (forall dom'. HiddenClockResetEnable dom' => Signal dom' addr -> Signal dom' wr -> Signal dom' a) -> DSignal dom d addr -> DSignal dom d wr -> DSignal dom (d + 1) a

delayedBlockRam1 :: (1 <= n, Enum addr, NFDataX addr, NFDataX a, HiddenClockResetEnable dom) => ResetStrategy r -> SNat n -> a -> DSignal dom d addr -> DSignal dom d (Maybe (addr, a)) -> DSignal dom (d + 1) a

sharedDelayed :: (KnownNat k, KnownNat n, HiddenClockResetEnable dom) => (DSignal dom d (Maybe addr) -> DSignal dom (d + k) a) -> Vec (n + 1) (DSignal dom d (Maybe addr)) -> Vec (n + 1) (DSignal dom (d + k) (Maybe a))

sharedDelayedRW :: (KnownNat k, KnownNat n, HiddenClockResetEnable dom) => (DSignal dom d addr -> DSignal dom d (Maybe wr) -> DSignal dom (d + k) a) -> Vec (n + 1) (DSignal dom d (Maybe (addr, Maybe wr))) -> Vec (n + 1) (DSignal dom (d + k) (Maybe a))

delayedRegister :: (NFDataX a, HiddenClockResetEnable dom) => a -> (DSignal dom d a -> DSignal dom d a) -> DSignal dom (d + 1) a

liftD :: HiddenClockResetEnable dom => (forall dom'. HiddenClockResetEnable dom' => Signal dom' a -> Signal dom' b) -> DSignal dom d a -> DSignal dom d b

liftD2 :: HiddenClockResetEnable dom => (forall dom'. HiddenClockResetEnable dom' => Signal dom' a -> Signal dom' b -> Signal dom' c) -> DSignal dom d a -> DSignal dom d b -> DSignal dom d c

matchDelay :: (KnownNat d, NFDataX a, HiddenClockResetEnable dom) => DSignal dom d any -> a -> Signal dom a -> Signal dom a