| Safe Haskell | Safe |
|---|---|
| Language | Haskell2010 |
RiscV.RV32I
Contents
- data Register
- data Instr
- data RegisterImmediateInstr
- data IOpcode
- data ShiftOpcode
- data RegisterRegisterInstr = RInstr !ROpcode !Register !Register !Register
- data ROpcode
- data JumpInstr
- data BranchInstr = Branch !Word20 !BranchCond !Register !Register
- data BranchCond
- data MemoryInstr
- data Width
- data LoadWidth
- data SynchronizationInstr
- data SyncOrdering = SyncOrd {
- deviceInput :: !Bool
- deviceOutput :: !Bool
- memoryReads :: !Bool
- memoryWrites :: !Bool
- data CSRInstr
- data CSRIOpcode
- data CSRROpcode
- data EnvironmentInstr
- newtype Word5 = Word5 Word8
- newtype Word12 = Word12 Word16
- newtype Word20 = Word20 Word32
Documentation
Register 1-31 are general-purpose registers holding integer values.
Register 0 is hardwired to the constant 0.
Integer Register-Immediate Instructions
Integer Register-Register Instructions
Control Transfer Instructions
data BranchInstr Source #
Constructors
| Branch !Word20 !BranchCond !Register !Register |
Load and Store Instructions
data MemoryInstr Source #
Constructors
| Width !Width | |
| HalfUnsigned | |
| ByteUnsigned |
Memory Synchronization Instructions
data SynchronizationInstr Source #
Constructors
| FENCE !SyncOrdering !SyncOrdering | |
| FENCEI |
data SyncOrdering Source #
Constructors
| SyncOrd | |
Fields
| |
Control and Status Register Instructions
Control and Status Register Instructions
Constructors
| CSRRInstr !CSRROpcode !Register !Register | |
| CSRIInstr !CSRROpcode !Word5 !Register |
data CSRIOpcode Source #
Control and status register instruction opcode using an immediate
data CSRROpcode Source #
Control and status register instruction opcode using a register
Environment Call and Breakpoints
data EnvironmentInstr Source #