Lava

Xilinx Lava is a library for FPGA circuit design with a focus on circuit layout.

Lava Gates

LUT-based gates

inv

Arguments

:: Bit

The input i0

-> Out Bit

The output o

The inv function implements an invertor explicitly with a LUT1.

and2

Arguments

:: (Bit, Bit)

inputs (i0, i1)

-> Out Bit

output o

The and2 function implements an AND gate explicitly with a LUT2.

or2

Arguments

:: (Bit, Bit)

inputs (i0, i1)

-> Out Bit

output o

The or2 function implements an OR gate explicitly with a LUT2.

nor2

Arguments

:: (Bit, Bit)

inputs (i0, i1)

-> Out Bit

output o

The nor2 function implements an NOR gate explicitly with a LUT2.

xor2

Arguments

:: (Bit, Bit)

inputs (i0, i1)

-> Out Bit

output o

The xor2 function implements an XOR gate explicitly with a LUT2.

xnor2

Arguments

:: (Bit, Bit)

inputs (i0, i1)

-> Out Bit

output o

The xnor2 function implements an XOR gate explicitly with a LUT2.

Carry-chain elements

muxcy

Arguments

:: Bit

ci

-> Bit

di

-> Bit

s

-> Out Bit

o

muxcy_d :: Bit -> Bit -> Bit -> Out (Bit, Bit)

muxcy_l :: Bit -> Bit -> Bit -> Out Bit

muxf5 :: Bit -> Bit -> Bit -> Out Bit

muxf5_d :: Bit -> Bit -> Bit -> Out (Bit, Bit)

muxf5_l :: Bit -> Bit -> Bit -> Out Bit

muxf6 :: Bit -> Bit -> Bit -> Out Bit

muxf6_d :: Bit -> Bit -> Bit -> Out (Bit, Bit)

muxf6_l :: Bit -> Bit -> Bit -> Out Bit

muxf7 :: Bit -> Bit -> Bit -> Out Bit

muxf7_d :: Bit -> Bit -> Bit -> Out (Bit, Bit)

muxf7_l :: Bit -> Bit -> Bit -> Out Bit

muxf8 :: Bit -> Bit -> Bit -> Out Bit

muxf8_d :: Bit -> Bit -> Bit -> Out (Bit, Bit)

muxf8_l :: Bit -> Bit -> Bit -> Out Bit

xorcy :: Bit -> Bit -> Out Bit

xorcy_d :: Bit -> Bit -> Out (Bit, Bit)

xorcy_l :: Bit -> Bit -> Out Bit

Flip-flops

fd :: Bit -> Bit -> Out Bit

fdc :: Bit -> Bit -> Bit -> Out Bit

fdc_1 :: Bit -> Bit -> Bit -> Out Bit

fdce :: Bit -> Bit -> Bit -> Bit -> Out Bit

fdce_1 :: Bit -> Bit -> Bit -> Bit -> Out Bit

fdcp :: Bit -> Bit -> Bit -> Bit -> Out Bit

fdcpe :: Bit -> Bit -> Bit -> Bit -> Bit -> Out Bit

fdcpe_1 :: Bit -> Bit -> Bit -> Bit -> Bit -> Out Bit

Shift-register primitives

srl16e

Arguments

:: Bit

d

-> Bit

clk

-> Bit

ce

-> Bit

a0

-> Bit

a1

-> Bit

a2

-> Bit

a3

-> Out Bit

q

16-bit shift register look-up table with clock enable

Gates implemented in place of a slice latch

and2b1l

Arguments

:: Bit

di

-> Bit

sri

-> Out Bit

o

Two input and gate implemented in place of a slice latch

or2l

Arguments

:: Bit

di

-> Bit

sri

-> Out Bit

o

Two input and gate implemented in place of a slice latch

Buffers

ibufg

Arguments

:: Bit

i

-> Out Bit

o

Dedicated input clock buffer

bufg

Arguments

:: Bit

i

-> Out Bit

o

Global clock buffer

bufgp

Arguments

:: Bit

i

-> Out Bit

o

Global clock buffer

obufg

Arguments

:: Bit

i

-> Out Bit

o

Output buffer

Double data rate (DDR) components

obufds

Arguments

:: Bit

i

-> Out (Bit, Bit)

(o, ob)

Output buffer

Lava Combinators

Serial composition combinators

(>->) :: (a -> Out b) -> (b -> Out c) -> a -> Out c

Serial composition with horizontal left to right layout

(>|>) :: (a -> Out b) -> (b -> Out c) -> a -> Out c

Serial composition with overly layout

Parallel composition combinators

replicateHorizontal :: Int -> (a -> Out a) -> a -> Out a

Repeated serial composition (left to right)

par2 :: (a -> Out c) -> (b -> Out d) -> (a, b) -> Out (c, d)

Horizontal parallel composition of two circuits

hpar :: [a -> Out b] -> [a] -> Out [b]

Horizontal parallel composition of a list of circuits

hparN :: Int -> (a -> Out b) -> [a] -> Out [b]

Horizontal repeated parallel composition of a circuit

Wiring combinators

fork2 :: a -> Out (a, a)

Splits a wire into two

listToPair :: [a] -> Out (a, a)

Converts a two element list into a pair

pairToList :: (a, a) -> Out [a]

Converts a par into a list containing two elements

ziP :: ([a], [b]) -> Out [(a, b)]

Takes a pair of lists and returns a zipped list of pairs

unziP :: [(a, b)] -> Out ([a], [b])

Takes a list of pairs and unzips it into a pair of lists

zipList :: [[a]] -> Out [[a]]

Takes a list containing two elements and returns a list of lists where each element is a two element list

unzipList :: [[a]] -> Out [[a]]

Undo the zipList operation

fstListPair :: [a] -> a

sndListPair :: [a] -> a

pair :: [a] -> Out [[a]]

This makes pairs out of consequetive members of an even length list.

unpair :: [[a]] -> Out [a]

Takes a list of pairs and returns a flattend list

halve :: [a] -> Out ([a], [a])

Tales a list and returns a pair containing the two halves of the list

unhalve :: ([a], [a]) -> Out [a]

Take a pair containing two list halves and undoes the halve

halveList :: [a] -> Out [[a]]

Halves the input list into a list containign the two halves

unhalveList :: [[a]] -> Out [a]

Undoes halveList

chop :: Int -> [a] -> Out [[a]]

Chops a list into chunks

concaT :: [[a]] -> Out [a]

Takes a list of lists and returns their concatenation

fstList :: ([a] -> Out [a]) -> [a] -> Out [a]

Applies a circuit to the first halve of a list

sndList :: ([a] -> Out [a]) -> [a] -> Out [a]

Applies a circuit to the second halve of a list

fsT :: (a -> Out b) -> (a, c) -> Out (b, c)

Applies a circuit to the first element of a pair

snD :: (b -> Out c) -> (a, b) -> Out (a, c)

Applies a circuit to the second element of a pair

reversE :: [a] -> Out [a]

Circuit input/output ports

inputPort :: String -> NetType -> Out Bit

inputPort creates a single bit input port

inputBitVec :: String -> NetType -> Out [Bit]

inputBitVec creates a bit-vector input port

outputPort :: String -> NetType -> Bit -> Out ()

outputPort creates a single bit output port

outputBitVec :: String -> NetType -> [Bit] -> Out ()

outputBitVec creates a bit-vector output port

data Dir

Constructors

To

Downto

Instances

Eq Dir

Show Dir

data NetType

Constructors

BitType

BitVec Int Dir Int

Instances

Eq NetType

Show NetType

data Netlist

type Out a = State Netlist a

type Bit = Int

Generating a Lava netlist

computeNetlist :: Out () -> Netlist

putXilinxVHDL :: String -> Netlist -> IO ()

Adding new primitive gates to the Lava system

primitiveGate

Arguments

:: String

The name of the component

-> [(String, Bit)]

name of input ports with argument nets

-> [String]

name of output ports

-> Maybe (Int, Int)

optional size information for layout

-> Out [Bit]

a list of output nets from this component

primitiveGate adds a primitive gate

Getting the Lava version number

lavaVersion :: (Int, Int, Int, Int)

This function defines the version of Lava which should correspond to the Cabal version.