Lava.Vhdl
Documentation
Arguments
| :: Generic a | |
| => String | The name of VHDL entity, which is also the name of the directory that the output files are written to. |
| -> a | The Bit-structure that is turned into VHDL. |
| -> a | Names for the outputs of the circuit. |
| -> IO () |
For example, the function
halfAdd :: Bit -> Bit -> (Bit, Bit)
halfAdd a b = (sum, carry)
where
sum = a <#> b
carry = a <&> b
can be converted to a VHDL entity with inputs named a and b and
outputs named sum and carry.
synthesiseHalfAdd :: IO ()
synthesiseHalfAdd =
writeVhdl "HalfAdd"
(halfAdd (name "a") (name "b"))
(name "sum", name "carry")
The function writeVhdl assumes that the part (FPGA chip) you are
targetting is the Virtex-5-110t-ff1136-1, because that is what sits
at my desk. This is only important if your design contains RAMs.
If your design does contain RAMs, and you wish to target a different
part, then use the writeVhdlForPart function. Xilinx's fault!
Arguments
| :: Generic a | |
| => Part | Part (FPGA chip) being targetted. |
| -> String | The name of VHDL entity, which is also the name of the directory that the output files are written to. |
| -> a | The Bit-structure that is turned into VHDL. |
| -> a | Names for the outputs of the circuit. |
| -> IO () |
Like writeVhdl, but allows the target part (FPGA chip) to be specified.
For example:
v5110t :: Part
v5110t =
Part {
partName = "xc5vlx110t"
, partFamily = "virtex5"
, partPackage = "ff1136"
, partSpeedGrade = "-1"
}
Constructors
| Part | |
Fields
| |