ForSyDe.Backend.VHDL

This module provides the VHDL backend of ForSyDe's embedded compiler

Documentation

writeVHDL :: SysDef a -> IO ()

Given a System Definition whose name is a valid VHDL _basic_ identifier (call it "A") generate A.vhd in current working directory using default compilation options. Imp: the input and output signal names of A must be valid VHDL identifiers (basic or extended) and different to clk and reset which are reserved for the main clock and reset signals

writeVHDLOps :: VHDLOps -> SysDef a -> IO ()

writeVHDL-alternative which allows setting VHDL compilation options.

writeAndModelsimVHDL

Arguments

:: SysFunToIOSimFun sysF simF

=> Maybe Int

Number of cycles to simulate if Nothing the number will be determined by the length of the input stimulti. Useful when the system to simulate doesn't have inputs or the inputs provided are infinite

-> SysDef sysF

system definition to simulate

-> simF

Generate a function which, given a system definition and some simulation stimuli:

1. Writes a VHDL model of the system
2. Simulates the VHDL model with Modelsim getting the results back to Haskell

writeAndModelsimVHDLOps :: SysFunToIOSimFun sysF simF => VHDLOps -> Maybe Int -> SysDef sysF -> simF

VHDLOps-alternative of writeAndModelsimVHDL, note that compileModelSim will implicitly be set to True

data VHDLOps

VHDL Compilation options

Constructors

VHDLOps

Fields

debugVHDL :: VHDLDebugLevel

Debug mode

recursivityVHDL :: VHDLRecursivity

execQuartus :: Maybe QuartusOps

Analyze the generated code with Quartus

compileModelsim :: Bool

Compile the generated code with Modelsim

Instances

Eq VHDLOps

Show VHDLOps

data QuartusOps

Options passed to Quartus II by the VHDL Backend. Most of them are optional and Quartus will use a default value.

It contains:

• What action to perform
• Optinally, the minimum acceptable clock frequency (fMax) expressed in MHz
• FPGA family and specific device model (both are independently optional).
• Pin assignments, in the form (VHDL Pin, FPGA Pin). Note that Quartus will automatically split composite VHDL ports

Constructors

QuartusOps

Fields

action :: QuartusAction

fMax :: Maybe Int

fpgaFamiliyDevice :: Maybe (String, Maybe String)

pinAssigs :: [(String, String)]

Instances

Eq QuartusOps

Show QuartusOps

data QuartusAction

Action to perform by Quartus

Constructors

AnalysisAndElaboration

Analysis and eleboration flow

AnalysisAndSynthesis

Call map executable

FullCompilation

Compile flow

Instances

Eq QuartusAction

Show QuartusAction

checkSynthesisQuartus :: QuartusOps

Options to check if the model is synthesizable, all options except the action to take are set to default.

data VHDLDebugLevel

Debug level

Constructors

VHDLNormal

VHDLVerbose

Instances

Eq VHDLDebugLevel

Ord VHDLDebugLevel

Show VHDLDebugLevel

data VHDLRecursivity

Recursivity, should the parent systems of system instances be compiled as well?

Constructors

VHDLRecursive

VHDLNonRecursive

Instances

Eq VHDLRecursivity

Show VHDLRecursivity

defaultVHDLOps :: VHDLOps

Default traversing options