ForSyDe.Backend.VHDL

Given a System Definition whose name is a valid VHDL _basic_ identifier (call it "A") generate A.vhd in current working directory using default compilation options. Imp: the input and output signal names of A must be valid VHDL identifiers (basic or extended) and different to clk and reset which are reserved for the main clock and reset signals

writeVHDLOps :: VHDLOps -> SysDef a -> IO ()

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writeVHDL-alternative which allows setting VHDL compilation options.

writeAndModelsimVHDL

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:: SysFunToIOSimFun sysF simF
=> Maybe Int	Number of cycles to simulate if `Nothing` the number will be determined by the length of the input stimulti. Useful when the system to simulate doesn't have inputs or the inputs provided are infinite
-> SysDef sysF	system definition to simulate
-> simF
Generate a function which, given a system definition and some simulation stimuli: Writes a VHDL model of the system Simulates the VHDL model with Modelsim getting the results back to Haskell

writeAndModelsimVHDLOps :: SysFunToIOSimFun sysF simF => VHDLOps -> Maybe Int -> SysDef sysF -> simF

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VHDLOps-alternative of writeAndModelsimVHDL, note that compileModelSim will implicitly be set to True

data VHDLOps

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VHDL Compilation options

Constructors

VHDLOps

debugVHDL :: VHDLDebugLevel	Debug mode
recursivityVHDL :: VHDLRecursivity
execQuartus :: Maybe QuartusOps	Analyze the generated code with Quartus
compileModelsim :: Bool	Compile the generated code with Modelsim

Instances

Eq VHDLOps

Show VHDLOps

data QuartusOps

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Options passed to Quartus II by the VHDL Backend. Most of them are optional and Quartus will use a default value.

It contains:

What action to perform
Optinally, the minimum acceptable clock frequency (fMax) expressed in MHz
FPGA family and specific device model (both are independently optional).
Pin assignments, in the form (VHDL Pin, FPGA Pin). Note that Quartus will automatically split composite VHDL ports

Constructors

QuartusOps