ForSyDe-3.0: ForSyDe's Haskell-embedded Domain Specific Language.Source codeContentsIndex
This module provides the VHDL backend of ForSyDe's embedded compiler
writeVHDL :: SysDef a -> IO ()
writeVHDLOps :: VHDLOps -> SysDef a -> IO ()
writeAndModelsimVHDL :: SysFunToIOSimFun sysF simF => Maybe Int -> SysDef sysF -> simF
writeAndModelsimVHDLOps :: SysFunToIOSimFun sysF simF => VHDLOps -> Maybe Int -> SysDef sysF -> simF
data VHDLOps = VHDLOps {
debugVHDL :: VHDLDebugLevel
recursivityVHDL :: VHDLRecursivity
execQuartus :: Maybe QuartusOps
compileModelsim :: Bool
data QuartusOps = QuartusOps {
action :: QuartusAction
fMax :: Maybe Int
fpgaFamiliyDevice :: Maybe (String, Maybe String)
pinAssigs :: [(String, String)]
data QuartusAction
= AnalysisAndElaboration
| AnalysisAndSynthesis
| FullCompilation
checkSynthesisQuartus :: QuartusOps
data VHDLDebugLevel
= VHDLNormal
| VHDLVerbose
data VHDLRecursivity
= VHDLRecursive
| VHDLNonRecursive
defaultVHDLOps :: VHDLOps
writeVHDL :: SysDef a -> IO ()Source
Given a System Definition whose name is a valid VHDL _basic_ identifier (call it "A") generate A.vhd in current working directory using default compilation options. Imp: the input and output signal names of A must be valid VHDL identifiers (basic or extended) and different to clk and reset which are reserved for the main clock and reset signals
writeVHDLOps :: VHDLOps -> SysDef a -> IO ()Source
writeVHDL-alternative which allows setting VHDL compilation options.
:: SysFunToIOSimFun sysF simF
=> Maybe IntNumber of cycles to simulate if Nothing the number will be determined by the length of the input stimulti. Useful when the system to simulate doesn't have inputs or the inputs provided are infinite
-> SysDef sysFsystem definition to simulate
-> simF

Generate a function which, given a system definition and some simulation stimuli:

  1. Writes a VHDL model of the system
  2. Simulates the VHDL model with Modelsim getting the results back to Haskell
writeAndModelsimVHDLOps :: SysFunToIOSimFun sysF simF => VHDLOps -> Maybe Int -> SysDef sysF -> simFSource
VHDLOps-alternative of writeAndModelsimVHDL, note that compileModelSim will implicitly be set to True
data VHDLOps Source
VHDL Compilation options
debugVHDL :: VHDLDebugLevelDebug mode
recursivityVHDL :: VHDLRecursivity
execQuartus :: Maybe QuartusOpsAnalyze the generated code with Quartus
compileModelsim :: BoolCompile the generated code with Modelsim
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data QuartusOps Source

Options passed to Quartus II by the VHDL Backend. Most of them are optional and Quartus will use a default value.

It contains:

  • What action to perform
  • Optinally, the minimum acceptable clock frequency (fMax) expressed in MHz
  • FPGA family and specific device model (both are independently optional).
  • Pin assignments, in the form (VHDL Pin, FPGA Pin). Note that Quartus will automatically split composite VHDL ports
action :: QuartusAction
fMax :: Maybe Int
fpgaFamiliyDevice :: Maybe (String, Maybe String)
pinAssigs :: [(String, String)]
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data QuartusAction Source
Action to perform by Quartus
AnalysisAndElaborationAnalysis and eleboration flow
AnalysisAndSynthesisCall map executable
FullCompilationCompile flow
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checkSynthesisQuartus :: QuartusOpsSource
Options to check if the model is synthesizable, all options except the action to take are set to default.
data VHDLDebugLevel Source
Debug level
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data VHDLRecursivity Source
Recursivity, should the parent systems of system instances be compiled as well?
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defaultVHDLOps :: VHDLOpsSource
Default traversing options
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