Copyright | (c) Marc Fontaine 2017 |
---|---|
License | BSD3 |
Maintainer | Marc.Fontaine@gmx.de |
Stability | experimental |
Portability | GHC-only |
Safe Haskell | None |
Language | Haskell2010 |
STM32.RCC
Description
Clock control and resetting parts of the hardware.
Documentation
set_HSE_OFF :: MI () Source #
set_HSE_ON :: MI () Source #
set_HSE_Bypass :: MI () Source #
peripheralClockOn :: Peripheral -> MI () Source #
peripheralClockOff :: Peripheral -> MI () Source #
peripheralClock :: Bool -> Peripheral -> MI () Source #
peripheralReset :: Bool -> Peripheral -> MI () Source #
peripheralResetToggle :: Peripheral -> MI () Source #
data SYSCLK_Div Source #
Constructors
SYSCLK_Div1 | |
SYSCLK_Div2 | |
SYSCLK_Div4 | |
SYSCLK_Div8 | |
SYSCLK_Div16 | |
SYSCLK_Div64 | |
SYSCLK_Div128 | |
SYSCLK_Div256 | |
SYSCLK_Div512 |
Instances
hCLKConfig :: SYSCLK_Div -> MI () Source #
Constructors
HCLK_Div1 | |
HCLK_Div2 | |
HCLK_Div4 | |
HCLK_Div8 | |
HCLK_Div16 |
pCLK1Config :: HCLK_Div -> MI () Source #
pCLK2Config :: HCLK_Div -> MI () Source #
Constructors
PLLSource_HSI_Div2 | |
PLLSource_HSE_Div1 | |
PLLSource_HSE_Div2 |
data SYSCLKSource Source #
Constructors
SYSCLKSource_HSI | |
SYSCLKSource_HSE | |
SYSCLKSource_PLLCLK |
Instances
sysCLKConfig :: SYSCLKSource -> MI () Source #
pllCmdEnable :: MI () Source #
setDefaultClocks :: MI () Source #
rtcClockConfig :: RtcClockSource -> MI () Source #