Wired-0.2: Wire-aware hardware descriptionSource codeContentsIndex
Lava.Internal
Synopsis
data Signal
= PrimInpSig PrimInpId
| CellSig CellId OutPin
data Declaration lib
= PrimInput PrimInpId
| Cell CellId lib [Signal]
| Label Tag Signal
data DesignDB lib = DesignDB {
cellDB :: Map CellId (lib, [Signal])
fanoutDB :: Map Signal [(CellId, InPin)]
sigTagDB :: Map Signal [Tag]
tagSigDB :: Map Tag [Signal]
primIns :: [Signal]
}
class CellLibrary lib where
numIns :: lib -> InPin
numOuts :: lib -> OutPin
inPinName :: lib -> InPin -> Name
inPinId :: lib -> Name -> InPin
outPinName :: lib -> OutPin -> Name
outPinId :: lib -> Name -> OutPin
isFlop :: lib -> Bool
lava2000Interp :: Interpretation lib (Signal Bool)
cellInputs :: CellLibrary lib => CellId -> lib -> [(CellId, InPin)]
cellOutputs :: CellLibrary lib => CellId -> lib -> [Signal]
prop_validSignals :: CellLibrary lib => [Declaration lib] -> Bool
prop_validDecls :: CellLibrary lib => [Declaration lib] -> Bool
newtype Lava lib a = Lava {
unLava :: WriterT [Declaration lib] (State (PrimInpId, CellId)) a
}
runLava :: CellLibrary lib => Lava lib a -> (a, DesignDB lib)
class (Monad m, CellLibrary lib) => MonadLava lib m | m -> lib where
newPrimInpId :: m PrimInpId
newCellId :: m CellId
declare :: Declaration lib -> m ()
listenDecls :: m a -> m (a, [Declaration lib])
toLava :: m a -> Lava lib a
inputSig :: MonadLava lib m => m Signal
cellList :: MonadLava lib m => lib -> [Signal] -> m [Signal]
labelSig :: MonadLava lib m => Tag -> Signal -> m Signal
data Interpretation lib x = Interp {
defaultVal :: x
accumulator :: x -> x -> x
propagator :: lib -> [x] -> [Maybe x]
}
type InterpDesignDB lib x = (DesignDB lib, Map Signal x)
lookupTag :: Tag -> InterpDesignDB lib x -> [x]
depthInterp :: CellLibrary lib => Interpretation lib Int
hasLoopDB :: CellLibrary lib => Bool -> DesignDB lib -> Bool
hasLoop :: MonadLava lib m => m a -> Bool
hasCombLoop :: MonadLava lib m => m a -> Bool
data PortTree s
= One {
unOne :: s
}
| List [PortTree s]
class Port p s | p -> s where
port :: p -> PortTree s
unport :: PortTree s -> p
class Port p s => PortStruct p s t | p -> s t, s t -> p
mapPort :: (PortStruct pa sa t, PortStruct pb sb t) => (sa -> sb) -> pa -> pb
mapPortM :: (PortStruct pa sa t, PortStruct pb sb t, Monad m) => (sa -> m sb) -> pa -> m pb
class Port p s => PortFixed p s | p -> s where
lengthFP :: Res p Int
fromListFP :: [s] -> p
askSig :: Interpretation lib x -> Signal -> Knot Signal x x
tellSigs :: Interpretation lib x -> [Signal] -> [Maybe x] -> Knot Signal x ()
interpretCells :: forall lib x. CellLibrary lib => Interpretation lib x -> [(Signal, x)] -> [(CellId, (lib, [Signal]))] -> Map Signal x
interpret__ :: CellLibrary lib => Interpretation lib x -> [(Signal, x)] -> (PortTree Signal, DesignDB lib) -> (PortTree x, InterpDesignDB lib x)
interpret_ :: CellLibrary lib => Interpretation lib x -> [(Signal, x)] -> Lava lib (PortTree Signal) -> (PortTree x, InterpDesignDB lib x)
interpret :: (CellLibrary lib, PortStruct ps Signal t, PortStruct px x t) => Interpretation lib x -> Lava lib ps -> (px, InterpDesignDB lib x)
inputToSig :: PortTree x -> PortTree Signal
interpretFuncP :: CellLibrary lib => Interpretation lib x -> (PortTree Signal -> Lava lib (PortTree Signal)) -> PortTree x -> (PortTree x, InterpDesignDB lib x)
interpretFunc :: (CellLibrary lib, PortStruct pxi x ti, PortStruct psi Signal ti, PortStruct pso Signal to, PortStruct pxo x to) => Interpretation lib x -> (psi -> Lava lib pso) -> pxi -> (pxo, InterpDesignDB lib x)
input :: forall lib m p. (MonadLava lib m, PortFixed p Signal) => m p
inputList :: (MonadLava lib m, PortFixed p Signal) => Int -> m [p]
cell :: forall m lib pi po. (MonadLava lib m, PortFixed pi Signal, PortFixed po Signal) => lib -> pi -> m po
sourceCell :: (MonadLava lib m, PortFixed p Signal) => lib -> m p
sinkCell :: (MonadLava lib m, PortFixed p Signal) => lib -> p -> m ()
physCell :: MonadLava lib m => lib -> a -> m a
label :: (MonadLava lib m, PortStruct p Signal t) => Tag -> p -> m p
toLava2000 :: (MonadLava lib m, PortStruct pli (Signal Bool) ti, PortStruct psi Signal ti, PortStruct pso Signal to, PortStruct plo (Signal Bool) to) => (psi -> m pso) -> pli -> plo
simulateSeq :: (MonadLava lib m, PortStruct pni Int ti, PortStruct psi Signal ti, PortStruct pso Signal to, PortStruct pno Int to) => (psi -> m pso) -> [pni] -> [pno]
simulate :: (MonadLava lib m, PortStruct pni Int ti, PortStruct psi Signal ti, PortStruct pso Signal to, PortStruct pno Int to) => (psi -> m pso) -> pni -> pno
encodeBin :: Int -> Int -> [Int]
decodeBin :: [Int] -> Int
verify :: forall lib m ps. (MonadLava lib m, PortFixed ps Signal) => (ps -> m Signal) -> IO ()
depth :: (MonadLava lib m, PortStruct ps Signal t, PortStruct pd Int t) => m ps -> (pd, InterpDesignDB lib Int)
fanout :: MonadLava lib m => m a -> InterpDesignDB lib Int
size :: MonadLava lib m => m p -> Int
Documentation
data Signal Source
Identifies a driver in the circuit. A driver is either a primary input or an output pin of a cell.
Constructors
PrimInpSig PrimInpId
CellSig CellId OutPin
show/hide Instances
data Declaration lib Source
Constructors
PrimInput PrimInpId
Cell CellId lib [Signal]
Label Tag Signal
show/hide Instances
Eq lib => Eq (Declaration lib)
Show lib => Show (Declaration lib)
data DesignDB lib Source
Constructors
DesignDB
cellDB :: Map CellId (lib, [Signal])
fanoutDB :: Map Signal [(CellId, InPin)]
sigTagDB :: Map Signal [Tag]
tagSigDB :: Map Tag [Signal]
primIns :: [Signal]
show/hide Instances
Eq lib => Eq (DesignDB lib)
Show lib => Show (DesignDB lib)
class CellLibrary lib whereSource
Methods
numIns :: lib -> InPinSource
numOuts :: lib -> OutPinSource
inPinName :: lib -> InPin -> NameSource
inPinId :: lib -> Name -> InPinSource
outPinName :: lib -> OutPin -> NameSource
outPinId :: lib -> Name -> OutPinSource
isFlop :: lib -> BoolSource
lava2000Interp :: Interpretation lib (Signal Bool)Source
show/hide Instances
cellInputs :: CellLibrary lib => CellId -> lib -> [(CellId, InPin)]Source
cellOutputs :: CellLibrary lib => CellId -> lib -> [Signal]Source
prop_validSignals :: CellLibrary lib => [Declaration lib] -> BoolSource
prop_validDecls :: CellLibrary lib => [Declaration lib] -> BoolSource
newtype Lava lib a Source
Constructors
Lava
unLava :: WriterT [Declaration lib] (State (PrimInpId, CellId)) a
show/hide Instances
CellLibrary lib => MonadLava lib (Lava lib)
Monad (Lava lib)
MonadFix (Lava lib)
runLava :: CellLibrary lib => Lava lib a -> (a, DesignDB lib)Source
class (Monad m, CellLibrary lib) => MonadLava lib m | m -> lib whereSource
Methods
newPrimInpId :: m PrimInpIdSource
newCellId :: m CellIdSource
declare :: Declaration lib -> m ()Source
listenDecls :: m a -> m (a, [Declaration lib])Source
toLava :: m a -> Lava lib aSource
show/hide Instances
CellLibrary lib => MonadLava lib (Lava lib)
MonadLava lib m => MonadLava lib (LayoutT s b m)
inputSig :: MonadLava lib m => m SignalSource
cellList :: MonadLava lib m => lib -> [Signal] -> m [Signal]Source
labelSig :: MonadLava lib m => Tag -> Signal -> m SignalSource
data Interpretation lib x Source
Constructors
Interp
defaultVal :: x
accumulator :: x -> x -> x
propagator :: lib -> [x] -> [Maybe x]
type InterpDesignDB lib x = (DesignDB lib, Map Signal x)Source
lookupTag :: Tag -> InterpDesignDB lib x -> [x]Source
depthInterp :: CellLibrary lib => Interpretation lib IntSource
hasLoopDB :: CellLibrary lib => Bool -> DesignDB lib -> BoolSource
hasLoop :: MonadLava lib m => m a -> BoolSource
hasCombLoop :: MonadLava lib m => m a -> BoolSource
data PortTree s Source
Constructors
One
unOne :: s
List [PortTree s]
show/hide Instances
class Port p s | p -> s whereSource
Methods
port :: p -> PortTree sSource
unport :: PortTree s -> pSource
show/hide Instances
Port Bool Bool
Port Int Int
Port () ()
Port Time Time
Port Signal Signal
Port p s => Port ([] p) s
Port p s => Port (Maybe p) s
Port (Signal Bool) (Signal Bool)
(Port p1 s, Port p2 s) => Port (Either p1 p2) s
(Port p1 s, Port p2 s) => Port ((,) p1 p2) s
(Port p1 s, Port p2 s, Port p3 s) => Port ((,,) p1 p2 p3) s
(Port p1 s, Port p2 s, Port p3 s, Port p4 s) => Port ((,,,) p1 p2 p3 p4) s
class Port p s => PortStruct p s t | p -> s t, s t -> pSource
show/hide Instances
mapPort :: (PortStruct pa sa t, PortStruct pb sb t) => (sa -> sb) -> pa -> pbSource
mapPortM :: (PortStruct pa sa t, PortStruct pb sb t, Monad m) => (sa -> m sb) -> pa -> m pbSource
class Port p s => PortFixed p s | p -> s whereSource
Methods
lengthFP :: Res p IntSource
fromListFP :: [s] -> pSource
show/hide Instances
PortFixed Signal Signal
(PortFixed p1 s, PortFixed p2 s) => PortFixed ((,) p1 p2) s
(PortFixed p1 s, PortFixed p2 s, PortFixed p3 s) => PortFixed ((,,) p1 p2 p3) s
(PortFixed p1 s, PortFixed p2 s, PortFixed p3 s, PortFixed p4 s) => PortFixed ((,,,) p1 p2 p3 p4) s
askSig :: Interpretation lib x -> Signal -> Knot Signal x xSource
tellSigs :: Interpretation lib x -> [Signal] -> [Maybe x] -> Knot Signal x ()Source
interpretCells :: forall lib x. CellLibrary lib => Interpretation lib x -> [(Signal, x)] -> [(CellId, (lib, [Signal]))] -> Map Signal xSource
interpret__ :: CellLibrary lib => Interpretation lib x -> [(Signal, x)] -> (PortTree Signal, DesignDB lib) -> (PortTree x, InterpDesignDB lib x)Source
interpret_ :: CellLibrary lib => Interpretation lib x -> [(Signal, x)] -> Lava lib (PortTree Signal) -> (PortTree x, InterpDesignDB lib x)Source
interpret :: (CellLibrary lib, PortStruct ps Signal t, PortStruct px x t) => Interpretation lib x -> Lava lib ps -> (px, InterpDesignDB lib x)Source
inputToSig :: PortTree x -> PortTree SignalSource
interpretFuncP :: CellLibrary lib => Interpretation lib x -> (PortTree Signal -> Lava lib (PortTree Signal)) -> PortTree x -> (PortTree x, InterpDesignDB lib x)Source
interpretFunc :: (CellLibrary lib, PortStruct pxi x ti, PortStruct psi Signal ti, PortStruct pso Signal to, PortStruct pxo x to) => Interpretation lib x -> (psi -> Lava lib pso) -> pxi -> (pxo, InterpDesignDB lib x)Source
input :: forall lib m p. (MonadLava lib m, PortFixed p Signal) => m pSource
inputList :: (MonadLava lib m, PortFixed p Signal) => Int -> m [p]Source
cell :: forall m lib pi po. (MonadLava lib m, PortFixed pi Signal, PortFixed po Signal) => lib -> pi -> m poSource
sourceCell :: (MonadLava lib m, PortFixed p Signal) => lib -> m pSource
sinkCell :: (MonadLava lib m, PortFixed p Signal) => lib -> p -> m ()Source
physCell :: MonadLava lib m => lib -> a -> m aSource
label :: (MonadLava lib m, PortStruct p Signal t) => Tag -> p -> m pSource
toLava2000 :: (MonadLava lib m, PortStruct pli (Signal Bool) ti, PortStruct psi Signal ti, PortStruct pso Signal to, PortStruct plo (Signal Bool) to) => (psi -> m pso) -> pli -> ploSource
simulateSeq :: (MonadLava lib m, PortStruct pni Int ti, PortStruct psi Signal ti, PortStruct pso Signal to, PortStruct pno Int to) => (psi -> m pso) -> [pni] -> [pno]Source
simulate :: (MonadLava lib m, PortStruct pni Int ti, PortStruct psi Signal ti, PortStruct pso Signal to, PortStruct pno Int to) => (psi -> m pso) -> pni -> pnoSource
encodeBin :: Int -> Int -> [Int]Source
encodeBin n x

Encodes the number x as a binary number of length n. The resulting list contains only zeroes and ones.

decodeBin :: [Int] -> IntSource
verify :: forall lib m ps. (MonadLava lib m, PortFixed ps Signal) => (ps -> m Signal) -> IO ()Source
depth :: (MonadLava lib m, PortStruct ps Signal t, PortStruct pd Int t) => m ps -> (pd, InterpDesignDB lib Int)Source
fanout :: MonadLava lib m => m a -> InterpDesignDB lib IntSource
size :: MonadLava lib m => m p -> IntSource
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