Safe Haskell | None |
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- data Signal
- data Declaration lib
- data DesignDB lib = DesignDB {}
- class CellLibrary lib where
- cellInputs :: CellLibrary lib => CellId -> lib -> [(CellId, InPin)]
- cellOutputs :: CellLibrary lib => CellId -> lib -> [Signal]
- prop_uniquePrimInputs :: [Declaration t] -> Bool
- prop_uniqueCells :: [Declaration t] -> Bool
- prop_correctCellInputs :: CellLibrary lib => [Declaration lib] -> Bool
- prop_validSignals :: CellLibrary lib => [Declaration lib] -> Bool
- prop_validDecls :: CellLibrary lib => [Declaration lib] -> Bool
- newtype Lava lib a = Lava {}
- runLava :: CellLibrary lib => Lava lib a -> (a, DesignDB lib)
- class (Monad m, CellLibrary lib) => MonadLava lib m | m -> lib where
- newPrimInpId :: m PrimInpId
- newCellId :: m CellId
- declare :: Declaration lib -> m ()
- listenDecls :: m a -> m (a, [Declaration lib])
- toLava :: m a -> Lava lib a
- inputSig :: MonadLava lib m => m Signal
- cellList :: MonadLava lib m => lib -> [Signal] -> m [Signal]
- labelSig :: MonadLava lib m => Tag -> Signal -> m Signal
- data Interpretation lib x = Interp {
- defaultVal :: x
- accumulator :: x -> x -> x
- propagator :: lib -> [x] -> [Maybe x]
- type InterpDesignDB lib x = (DesignDB lib, Map Signal x)
- lookupTag :: Tag -> InterpDesignDB lib x -> [x]
- depthInterp :: CellLibrary lib => Interpretation lib Int
- hasLoopDB :: CellLibrary lib => Bool -> DesignDB lib -> Bool
- hasLoop :: MonadLava lib m => m a -> Bool
- hasCombLoop :: MonadLava lib m => m a -> Bool
- data PortTree s
- class Port p s | p -> s where
- class Port p s => PortStruct p s t | p -> s t, s t -> p
- mapPort :: (PortStruct pa sa t, PortStruct pb sb t) => (sa -> sb) -> pa -> pb
- mapPortM :: (PortStruct pa sa t, PortStruct pb sb t, Monad m) => (sa -> m sb) -> pa -> m pb
- class Port p s => PortFixed p s | p -> s where
- lengthFP :: Res p Int
- fromListFP :: [s] -> p
- askSig :: Interpretation lib x -> Signal -> Knot Signal x x
- tellSigs :: Interpretation lib x -> [Signal] -> [Maybe x] -> Knot Signal x ()
- interpretCells :: forall lib x. CellLibrary lib => Interpretation lib x -> [(Signal, x)] -> [(CellId, (lib, [Signal]))] -> Map Signal x
- interpret__ :: CellLibrary lib => Interpretation lib x -> [(Signal, x)] -> (PortTree Signal, DesignDB lib) -> (PortTree x, InterpDesignDB lib x)
- interpret_ :: CellLibrary lib => Interpretation lib x -> [(Signal, x)] -> Lava lib (PortTree Signal) -> (PortTree x, InterpDesignDB lib x)
- interpret :: (CellLibrary lib, PortStruct ps Signal t, PortStruct px x t) => Interpretation lib x -> Lava lib ps -> (px, InterpDesignDB lib x)
- inputToSig :: PortTree x -> PortTree Signal
- interpretFuncP :: CellLibrary lib => Interpretation lib x -> (PortTree Signal -> Lava lib (PortTree Signal)) -> PortTree x -> (PortTree x, InterpDesignDB lib x)
- interpretFunc :: (CellLibrary lib, PortStruct pxi x ti, PortStruct psi Signal ti, PortStruct pso Signal to, PortStruct pxo x to) => Interpretation lib x -> (psi -> Lava lib pso) -> pxi -> (pxo, InterpDesignDB lib x)
- input :: forall lib m p. (MonadLava lib m, PortFixed p Signal) => m p
- inputList :: (MonadLava lib m, PortFixed p Signal) => Int -> m [p]
- cell :: forall m lib pi po. (MonadLava lib m, PortFixed pi Signal, PortFixed po Signal) => lib -> pi -> m po
- sourceCell :: (MonadLava lib m, PortFixed p Signal) => lib -> m p
- sinkCell :: (MonadLava lib m, PortFixed p Signal) => lib -> p -> m ()
- physCell :: MonadLava lib m => lib -> a -> m a
- label :: (MonadLava lib m, PortStruct p Signal t) => Tag -> p -> m p
- toLava2000 :: (MonadLava lib m, PortStruct pli (Signal Bool) ti, PortStruct psi Signal ti, PortStruct pso Signal to, PortStruct plo (Signal Bool) to) => (psi -> m pso) -> pli -> plo
- simulateSeq :: (MonadLava lib m, PortStruct pni Int ti, PortStruct psi Signal ti, PortStruct pso Signal to, PortStruct pno Int to) => (psi -> m pso) -> [pni] -> [pno]
- simulate :: (MonadLava lib m, PortStruct pni Int ti, PortStruct psi Signal ti, PortStruct pso Signal to, PortStruct pno Int to) => (psi -> m pso) -> pni -> pno
- encodeBin :: Int -> Int -> [Int]
- decodeBin :: [Int] -> Int
- prop_encodeBin :: Property
- prop_encodeDecodeBin :: Property
- checkAll :: IO ()
- verify :: forall lib m ps. (MonadLava lib m, PortFixed ps Signal) => (ps -> m Signal) -> IO ()
- depth :: (MonadLava lib m, PortStruct ps Signal t, PortStruct pd Int t) => m ps -> (pd, InterpDesignDB lib Int)
- fanout :: MonadLava lib m => m a -> InterpDesignDB lib Int
- size :: MonadLava lib m => m p -> Int
Documentation
Identifies a driver in the circuit. A driver is either a primary input or an output pin of a cell.
data Declaration lib Source
Eq lib => Eq (Declaration lib) | |
Show lib => Show (Declaration lib) |
class CellLibrary lib whereSource
cellInputs :: CellLibrary lib => CellId -> lib -> [(CellId, InPin)]Source
cellOutputs :: CellLibrary lib => CellId -> lib -> [Signal]Source
prop_uniquePrimInputs :: [Declaration t] -> BoolSource
prop_uniqueCells :: [Declaration t] -> BoolSource
prop_correctCellInputs :: CellLibrary lib => [Declaration lib] -> BoolSource
prop_validSignals :: CellLibrary lib => [Declaration lib] -> BoolSource
prop_validDecls :: CellLibrary lib => [Declaration lib] -> BoolSource
runLava :: CellLibrary lib => Lava lib a -> (a, DesignDB lib)Source
class (Monad m, CellLibrary lib) => MonadLava lib m | m -> lib whereSource
newPrimInpId :: m PrimInpIdSource
declare :: Declaration lib -> m ()Source
listenDecls :: m a -> m (a, [Declaration lib])Source
data Interpretation lib x Source
Interp | |
|
type InterpDesignDB lib x = (DesignDB lib, Map Signal x)Source
lookupTag :: Tag -> InterpDesignDB lib x -> [x]Source
depthInterp :: CellLibrary lib => Interpretation lib IntSource
hasCombLoop :: MonadLava lib m => m a -> BoolSource
class Port p s | p -> s whereSource
Port Bool Bool | |
Port Int Int | |
Port () () | |
Port Time Time | |
Port Signal Signal | |
Port p s => Port [p] s | |
Port p s => Port (Maybe p) s | |
Port (Signal Bool) (Signal Bool) | |
(Port p1 s, Port p2 s) => Port (Either p1 p2) s | |
(Port p1 s, Port p2 s) => Port (p1, p2) s | |
(Port p1 s, Port p2 s, Port p3 s) => Port (p1, p2, p3) s | |
(Port p1 s, Port p2 s, Port p3 s, Port p4 s) => Port (p1, p2, p3, p4) s |
class Port p s => PortStruct p s t | p -> s t, s t -> pSource
PortStruct Bool Bool () | |
PortStruct Int Int () | |
PortStruct () () () | |
PortStruct Time Time () | |
PortStruct Signal Signal () | |
PortStruct p s t => PortStruct [p] s [t] | |
PortStruct p s t => PortStruct (Maybe p) s (Maybe t) | |
PortStruct (Signal Bool) (Signal Bool) () | |
(PortStruct p1 s t1, PortStruct p2 s t2) => PortStruct (Either p1 p2) s (Either t1 t2) | |
(PortStruct p1 s t1, PortStruct p2 s t2) => PortStruct (p1, p2) s (t1, t2) | |
(PortStruct p1 s t1, PortStruct p2 s t2, PortStruct p3 s t3) => PortStruct (p1, p2, p3) s (t1, t2, t3) | |
(PortStruct p1 s t1, PortStruct p2 s t2, PortStruct p3 s t3, PortStruct p4 s t4) => PortStruct (p1, p2, p3, p4) s (t1, t2, t3, t4) |
mapPort :: (PortStruct pa sa t, PortStruct pb sb t) => (sa -> sb) -> pa -> pbSource
mapPortM :: (PortStruct pa sa t, PortStruct pb sb t, Monad m) => (sa -> m sb) -> pa -> m pbSource
interpretCells :: forall lib x. CellLibrary lib => Interpretation lib x -> [(Signal, x)] -> [(CellId, (lib, [Signal]))] -> Map Signal xSource
interpret__ :: CellLibrary lib => Interpretation lib x -> [(Signal, x)] -> (PortTree Signal, DesignDB lib) -> (PortTree x, InterpDesignDB lib x)Source
interpret_ :: CellLibrary lib => Interpretation lib x -> [(Signal, x)] -> Lava lib (PortTree Signal) -> (PortTree x, InterpDesignDB lib x)Source
interpret :: (CellLibrary lib, PortStruct ps Signal t, PortStruct px x t) => Interpretation lib x -> Lava lib ps -> (px, InterpDesignDB lib x)Source
inputToSig :: PortTree x -> PortTree SignalSource
interpretFuncP :: CellLibrary lib => Interpretation lib x -> (PortTree Signal -> Lava lib (PortTree Signal)) -> PortTree x -> (PortTree x, InterpDesignDB lib x)Source
interpretFunc :: (CellLibrary lib, PortStruct pxi x ti, PortStruct psi Signal ti, PortStruct pso Signal to, PortStruct pxo x to) => Interpretation lib x -> (psi -> Lava lib pso) -> pxi -> (pxo, InterpDesignDB lib x)Source
cell :: forall m lib pi po. (MonadLava lib m, PortFixed pi Signal, PortFixed po Signal) => lib -> pi -> m poSource
sourceCell :: (MonadLava lib m, PortFixed p Signal) => lib -> m pSource
toLava2000 :: (MonadLava lib m, PortStruct pli (Signal Bool) ti, PortStruct psi Signal ti, PortStruct pso Signal to, PortStruct plo (Signal Bool) to) => (psi -> m pso) -> pli -> ploSource
simulateSeq :: (MonadLava lib m, PortStruct pni Int ti, PortStruct psi Signal ti, PortStruct pso Signal to, PortStruct pno Int to) => (psi -> m pso) -> [pni] -> [pno]Source
simulate :: (MonadLava lib m, PortStruct pni Int ti, PortStruct psi Signal ti, PortStruct pso Signal to, PortStruct pno Int to) => (psi -> m pso) -> pni -> pnoSource
encodeBin :: Int -> Int -> [Int]Source
encodeBin n x
Encodes the number x
as a binary number of length n
. The resulting list
contains only zeroes and ones.
verify :: forall lib m ps. (MonadLava lib m, PortFixed ps Signal) => (ps -> m Signal) -> IO ()Source
depth :: (MonadLava lib m, PortStruct ps Signal t, PortStruct pd Int t) => m ps -> (pd, InterpDesignDB lib Int)Source
fanout :: MonadLava lib m => m a -> InterpDesignDB lib IntSource