clash-lib-0.5.2: CAES Language for Synchronous Hardware - As a Library

Copyright(C) 2015, University of Twente
LicenseBSD2 (see the file LICENSE)
MaintainerChristiaan Baaij <christiaan.baaij@gmail.com>
Safe HaskellNone
LanguageHaskell2010
Extensions
  • TemplateHaskell
  • OverloadedStrings
  • DisambiguateRecordFields
  • RecordWildCards
  • TupleSections

CLaSH.Driver.TopWrapper

Description

 

Synopsis

Documentation

data TopEntity Source

TopEntity specifications, fields are self-explanatory

Constructors

TopEntity 

Fields

t_name :: Text
 
t_inputs :: [Text]
 
t_outputs :: [Text]
 
t_extraIn :: [(Text, Int)]
 
t_extraOut :: [(Text, Int)]
 
t_clocks :: [ClockSource]
 

data ClockSource Source

A clock source

Constructors

ClockSource 

Fields

c_name :: Text

Component name

c_paths :: [ClockPath]

Number of clock paths

c_reset :: Maybe (Text, Text)

optional: Asynchronous reset input

c_lock :: Text

Port name that indicates clock is stable

c_sync :: Bool

optional: devices connected this clock source should be pulled out of reset in-sync

data ClockPath Source

A clock path

Constructors

ClockPath 

Fields

cp_inp :: Maybe (Text, Text)
 
cp_outp :: [(Text, Clock)]
 

data Clock Source

A clock

Constructors

Clk 

Fields

clk_name :: Text
 
clk_rate :: Int
 

generateTopEnt :: String -> IO (Maybe TopEntity) Source

Create a TopEntity data type from the JSON encoded .topentity file.

mkTopWrapper Source

Arguments

:: PrimMap 
-> Maybe TopEntity

TopEntity specifications

-> Component

Entity to wrap

-> Component 

Create a wrapper around a component, potentially initiating clock sources

extraIn :: Maybe TopEntity -> [(Identifier, HWType)] Source

Create extra input ports for the wrapper

extraOut :: Maybe TopEntity -> [(Identifier, HWType)] Source

Create extra output ports for the wrapper

mkInput :: [Identifier] -> (Identifier, HWType) -> Int -> ([Identifier], ([(Identifier, HWType)], ([Declaration], Identifier))) Source

Generate input port mappings

mkVectorChain :: Int -> HWType -> [Identifier] -> Expr Source

Create a Vector chain for a list of Identifiers

mkOutput :: [Identifier] -> (Identifier, HWType) -> Int -> ([Identifier], ([(Identifier, HWType)], ([Declaration], Identifier))) Source

Generate output port mappings

mkClocks :: PrimMap -> [(Identifier, HWType)] -> Maybe TopEntity -> [Declaration] Source

Create clock generators

mkClock :: ClockSource -> ([Declaration], (Identifier, [Clock], Bool)) Source

Create a single clock generator

clockPorts :: ClockPath -> ([(Identifier, Expr)], [Clock]) Source

Create a single clock path

mkResets :: PrimMap -> [(Identifier, HWType)] -> [(Identifier, [Clock], Bool)] -> [Declaration] Source

Generate resets

genSyncReset :: PrimMap -> Identifier -> Identifier -> Clock -> NetlistMonad [Declaration] Source

Generate a reset synchroniser that synchronously de-asserts an asynchronous reset signal

unsafeRunNetlist :: NetlistMonad a -> a Source

The NetListMonad is an transformer stack with IO at the bottom. So we must use unsafePerformIO.