Clash.Backend.Verilog

Generate Verilog for assorted Netlist datatypes

Documentation

data VerilogState

State for the VerilogM monad:

Instances

HasIdentifierSet VerilogState

Defined in Clash.Backend.Verilog

Methods

identifierSet :: Lens' VerilogState IdentifierSet

Backend VerilogState

Defined in Clash.Backend.Verilog

Methods

initBackend :: ClashOpts -> VerilogState

hdlKind :: VerilogState -> HDL

primDirs :: VerilogState -> IO [FilePath]

name :: VerilogState -> String

extension :: VerilogState -> String

extractTypes :: VerilogState -> HashSet HWType

genHDL :: ModName -> SrcSpan -> IdentifierSet -> Component -> Ap (State VerilogState) ((String, Doc), [(String, Doc)])

mkTyPackage :: ModName -> [HWType] -> Ap (State VerilogState) [(String, Doc)]

hdlType :: Usage -> HWType -> Ap (State VerilogState) Doc

hdlHWTypeKind :: HWType -> State VerilogState HWKind

hdlTypeErrValue :: HWType -> Ap (State VerilogState) Doc

hdlTypeMark :: HWType -> Ap (State VerilogState) Doc

hdlRecSel :: HWType -> Int -> Ap (State VerilogState) Doc

hdlSig :: Text -> HWType -> Ap (State VerilogState) Doc

genStmt :: Bool -> State VerilogState Doc

inst :: Declaration -> Ap (State VerilogState) (Maybe Doc)

expr :: Bool -> Expr -> Ap (State VerilogState) Doc

iwWidth :: State VerilogState Int

toBV :: HWType -> Text -> Ap (State VerilogState) Doc

fromBV :: HWType -> Text -> Ap (State VerilogState) Doc

hdlSyn :: State VerilogState HdlSyn

setModName :: ModName -> VerilogState -> VerilogState

setTopName :: Identifier -> VerilogState -> VerilogState

getTopName :: State VerilogState Identifier

setSrcSpan :: SrcSpan -> State VerilogState ()

getSrcSpan :: State VerilogState SrcSpan

blockDecl :: Identifier -> [Declaration] -> Ap (State VerilogState) Doc

addIncludes :: [(String, Doc)] -> State VerilogState ()

addLibraries :: [Text] -> State VerilogState ()

addImports :: [Text] -> State VerilogState ()

addAndSetData :: FilePath -> State VerilogState String

getDataFiles :: State VerilogState [(String, FilePath)]

addMemoryDataFile :: (String, String) -> State VerilogState ()

getMemoryDataFiles :: State VerilogState [(String, String)]

ifThenElseExpr :: VerilogState -> Bool

aggressiveXOptBB :: State VerilogState AggressiveXOptBB

renderEnums :: State VerilogState RenderEnums

domainConfigurations :: State VerilogState DomainMap

setDomainConfigurations :: DomainMap -> VerilogState -> VerilogState

include :: Monad m => [Text] -> Ap m Doc

uselibs :: Monad m => [Text] -> Ap m Doc

encodingNote :: Applicative m => HWType -> m Doc

exprLit :: Lens' s (Maybe (Maybe Int)) -> Maybe (HWType, Size) -> Literal -> Ap (State s) Doc

bits :: Lens' s (Maybe (Maybe Int)) -> [Bit] -> Ap (State s) Doc

bit_char :: Lens' s (Maybe (Maybe Int)) -> Bit -> Ap (State s) Doc

noEmptyInit :: (Monad m, Semigroup (m Doc)) => m Doc -> m Doc

split ranges

data Range

Range slice, can be contiguous, or split into multiple sub-ranges

Constructors

Contiguous Int Int

Split [(Int, Int, Provenance)]

continueWithRange

Arguments

:: [(Int, Int)]

Starts and ends

-> HWType

Type of the projection

-> Range

Range selected so far

-> (Range, HWType)

Select a sub-range from a range