clash-prelude-0.11.2: CAES Language for Synchronous Hardware - Prelude library

Copyright(C) 2015-2016 University of Twente
LicenseBSD2 (see the file LICENSE)
MaintainerChristiaan Baaij <>
Safe HaskellTrustworthy
  • Cpp
  • MonoLocalBinds
  • ScopedTypeVariables
  • AllowAmbiguousTypes
  • TypeFamilies
  • PolyKinds
  • DataKinds
  • FlexibleContexts
  • KindSignatures
  • TypeOperators
  • ExplicitNamespaces
  • ExplicitForAll
  • TypeApplications




Synchronizer circuits for safe clock domain crossings



dualFlipFlopSynchronizer Source #


:: SClock clk1

Clock to which the incoming data is synchronised

-> SClock clk2

Clock to which the outgoing data is synchronised

-> a

Initial value of the two synchronisation registers

-> Signal' clk1 a

Incoming data

-> Signal' clk2 a

Outgoing, synchronised, data

Synchroniser based on two sequentially connected flip-flops.

  • NB: This synchroniser can be used for bit-synchronization.
  • NB: Although this synchroniser does reduce metastability, it does not guarantee the proper synchronisation of a whole word. For example, given that the output is sampled twice as fast as the input is running, and we have two samples in the input stream that look like:


    But the circuit driving the input stream has a longer propagation delay on msb compared to the lsbs. What can happen is an output stream that looks like this:


    Where the level-change of the msb was not captured, but the level change of the lsbs were.

    If you want to have safe word-synchronisation use asyncFIFOSynchronizer.


asyncFIFOSynchronizer Source #


:: 2 <= addrSize 
=> SNat addrSize

Size of the internally used addresses, the FIFO contains 2^addrSize elements.

-> SClock wclk

Clock to which the write port is synchronised

-> SClock rclk

Clock to which the read port is synchronised

-> Signal' rclk Bool

Read request

-> Signal' wclk (Maybe a)

Element to insert

-> (Signal' rclk a, Signal' rclk Bool, Signal' wclk Bool)

(Oldest element in the FIFO, empty flag, full flag)

Synchroniser implemented as a FIFO around an asynchronous RAM. Based on the design described in CLaSH.Tutorial, which is itself based on the design described in

NB: This synchroniser can be used for word-synchronization.