CLaSH.Prelude

Documentation

(<^>)

Arguments

:: (Pack i, Pack o)

=> (s -> i -> (s, o))

Transfer function in mealy machine form

-> s

Initial state

-> SignalP i -> SignalP o

Synchronous function with input and output matching that of the mealy machine

Create a synchronous function from a combinational function describing a mealy machine

mac s (x,y) = (s',s)
  where
    s' = x * y + s

topEntity :: (Signal Int, Signal Int) -> Signal Int
topEntity = mac <^> 0

simulateP topEntity [(1,1),(2,2),(3,3),(4,4),... = [0,1,5,14,30,...

registerP :: Pack a => a -> SignalP a -> SignalP a

Create a register function for product-type like signals (e.g. '(Signal a, Signal b)')

rP :: (Signal Int,Signal Int) -> (Signal Int, Signal Int)
rP = registerP (8,8)

simulateP rP [(1,1),(2,2),(3,3),... = [(8,8),(1,1),(2,2),(3,3),...

newtype Comp a b

Arrow interface to synchronous functions

Constructors

C

Fields

asFunction :: Signal a -> Signal b

Instances

Arrow Comp

ArrowLoop Comp

Category * Comp

registerC :: a -> Comp a a

Create a register Component

rC :: Comp (Int,Int) (Int,Int)
rC = registerC (8,8)

simulateC rP [(1,1),(2,2),(3,3),... = [(8,8),(1,1),(2,2),(3,3),...

simulateC :: Comp a b -> [a] -> [b]

Simulate a Component given a list of samples

simulateC (registerC 8) [1, 2, 3, ... = [8, 1, 2, 3, ...

(^^^) :: (s -> i -> (s, o)) -> s -> Comp i o

Create a synchronous Component from a combinational function describing a mealy machine

mac s (x,y) = (s',s)
  where
    s' = x * y + s

topEntity :: Comp (Int,Int) Int
topEntity = mac ^^^ 0

simulateC topEntity [(1,1),(2,2),(3,3),(4,4),... = [0,1,5,14,30,...

blockRam

Arguments

:: forall n m a . (KnownNat n, KnownNat m, Pack a)

=> SNat n

Size n of the blockram

-> Signal (Unsigned m)

Write address w

-> Signal (Unsigned m)

Read address r

-> Signal Bool

Write enable

-> Signal a

Value to write (at address w)

-> Signal a

Value of the blockRAM at address r from the previous clock cycle

Create a blockRAM with space for n elements

bram40 :: Signal (Unsigned 6) -> Signal (Unsigned 6) -> Signal Bool -> Signal a -> Signal a
bram40 = blockRam d50

blockRamPow2

Arguments

:: (KnownNat n, KnownNat (2 ^ n), Pack a)

=> SNat (2 ^ n :: Nat)

Size 2^n of the blockram

-> Signal (Unsigned n)

Write address w

-> Signal (Unsigned n)

Read address r

-> Signal Bool

Write enable

-> Signal a

Value to write (at address w)

-> Signal a

Value of the blockRAM at address r from the previous clock cycle

Create a blockRAM with space for 2^n elements

bram32 :: Signal (Unsigned 5) -> Signal (Unsigned 5) -> Signal Bool -> Signal a -> Signal a
bram32 = blockRamPow2 d32

window :: (KnownNat (n + 1), Default a) => Signal a -> Vec ((n + 1) + 1) (Signal a)

Give a window over a Signal

window4 :: Signal Int -> Vec 4 (Signal Int)
window4 = window

simulateP window4 [1,2,3,4,5,... = [<1,0,0,0>,<2,1,0,0>,<3,2,1,0>,<4,3,2,1>,<5,4,3,2>,...

windowD :: (KnownNat (n + 1), Default a) => Signal a -> Vec (n + 1) (Signal a)

Give a delayed window over a Signal

windowD3 :: Signal Int -> Vec 3 (Signal Int)
windowD3 = windowD

simulateP windowD3 [1,2,3,4,... = [<0,0,0>,<1,0,0>,<2,1,0>,<3,2,1>,<4,3,2>,...