Copyright	(C) 2013-2016 University of Twente 2017 Google Inc.
License	BSD2 (see the file LICENSE)
Maintainer	Christiaan Baaij <christiaan.baaij@gmail.com>
Safe Haskell	Unsafe
Language	Haskell2010
Extensions	DataKinds TypeOperators ExplicitNamespaces

Clash.Explicit.Prelude

Contents

Creating synchronous sequential circuits
Synchronizer circuits for safe clock domain crossings
ROMs
- ROMs initialised with a data file
RAM primitives with a combinational read port
BlockRAM primitives
- BlockRAM primitives initialised with a data file
- BlockRAM read/write conflict resolution
Utility functions
Testbench functions
Exported modules

Description

This module defines the explicitly clocked counterparts of the functions defined in Clash.Prelude. Take a look at Clash.Signal.Explicit to see how you can make multi-clock designs.

Synopsis

Creating synchronous sequential circuits

mealy Source #

Arguments

:: Clock dom gated	`Clock` to synchronize to
-> Reset dom synchronous
-> (s -> i -> (s, o))	Transfer function in mealy machine form: `state -> input -> (newstate,output)`
-> s	Initial state
-> Signal dom i -> Signal dom o	Synchronous sequential function with input and output matching that of the mealy machine

Create a synchronous function from a combinational function describing a mealy machine

import qualified Data.List as L

macT
  :: Int        -- Current state
  -> (Int,Int)  -- Input
  -> (Int,Int)  -- (Updated state, output)
macT s (x,y) = (s',s)
  where
    s' = x * y + s

mac
  :: Clock domain Source
  -> Reset domain Asynchronous
  -> Signal domain (Int, Int)
  -> Signal domain Int
mac clk rst = mealy clk rst macT 0

>>> simulate (mac systemClockGen systemResetGen) [(1,1),(2,2),(3,3),(4,4)]
[0,1,5,14...
...

Synchronous sequential functions can be composed just like their combinational counterpart:

dualMac
  :: Clock domain gated -> Reset domain synchronous
  -> (Signal domain Int, Signal domain Int)
  -> (Signal domain Int, Signal domain Int)
  -> Signal domain Int
dualMac clk rst (a,b) (x,y) = s1 + s2
  where
    s1 = mealy clk rst mac 0 (bundle (a,x))
    s2 = mealy clk rst mac 0 (bundle (b,y))

mealyB Source #

Arguments

:: (Bundle i, Bundle o)
=> Clock dom gated
-> Reset dom synchronous
-> (s -> i -> (s, o))	Transfer function in mealy machine form: `state -> input -> (newstate,output)`
-> s	Initial state
-> Unbundled dom i -> Unbundled dom o	Synchronous sequential function with input and output matching that of the mealy machine

A version of mealy that does automatic Bundleing

Given a function f of type:

f :: Int -> (Bool,Int) -> (Int,(Int,Bool))

When we want to make compositions of f in g using mealy', we have to write:

g clk rst a b c = (b1,b2,i2)
  where
    (i1,b1) = unbundle (mealy clk rst f 0 (bundle (a,b)))
    (i2,b2) = unbundle (mealy clk rst f 3 (bundle (i1,c)))

Using mealyB' however we can write:

g clk rst a b c = (b1,b2,i2)
  where
    (i1,b1) = mealyB clk rst f 0 (a,b)
    (i2,b2) = mealyB clk rst f 3 (i1,c)

moore Source #

Arguments

:: Clock domain gated	`Clock` to synchronize to
-> Reset domain synchronous
-> (s -> i -> s)	Transfer function in moore machine form: `state -> input -> newstate`
-> (s -> o)	Output function in moore machine form: `state -> output`
-> s	Initial state
-> Signal domain i -> Signal domain o	Synchronous sequential function with input and output matching that of the moore machine

Create a synchronous function from a combinational function describing a moore machine

macT
  :: Int        -- Current state
  -> (Int,Int)  -- Input
  -> (Int,Int)  -- Updated state
macT s (x,y) = x * y + s

mac
  :: Clock mac Source
  -> Reset mac Asynchronous
  -> Signal mac (Int, Int)
  -> Signal mac Int
mac clk rst = moore clk rst macT id 0

>>> simulate (mac systemClockGen systemResetGen) [(1,1),(2,2),(3,3),(4,4)]
[0,1,5,14...
...

Synchronous sequential functions can be composed just like their combinational counterpart:

dualMac
  :: Clock domain gated
  -> Reset domain synchronous
  -> (Signal domain Int, Signal domain Int)
  -> (Signal domain Int, Signal domain Int)
  -> Signal domain Int
dualMac clk rst (a,b) (x,y) = s1 + s2
  where
    s1 = moore clk rst mac id 0 (bundle (a,x))
    s2 = moore clk rst mac id 0 (bundle (b,y))

mooreB Source #

Arguments

:: (Bundle i, Bundle o)
=> Clock domain gated
-> Reset domain synchronous
-> (s -> i -> s)	Transfer function in moore machine form: `state -> input -> newstate`
-> (s -> o)	Output function in moore machine form: `state -> output`
-> s	Initial state
-> Unbundled domain i -> Unbundled domain o	Synchronous sequential function with input and output matching that of the moore machine

A version of moore that does automatic Bundleing

Given a functions t and o of types:

t :: Int -> (Bool, Int) -> Int
o :: Int -> (Int, Bool)

When we want to make compositions of t and o in g using moore', we have to write:

g clk rst a b c = (b1,b2,i2)
  where
    (i1,b1) = unbundle (moore clk rst t o 0 (bundle (a,b)))
    (i2,b2) = unbundle (moore clk rst t o 3 (bundle (i1,c)))

Using mooreB' however we can write:

g clk rst a b c = (b1,b2,i2)
  where
    (i1,b1) = mooreB clk rst t o 0 (a,b)
    (i2,b2) = mooreB clk rst t o 3 (i1,c)

registerB :: Bundle a => Clock domain gated -> Reset domain synchronous -> a -> Unbundled domain a -> Unbundled domain a Source #

Create a register function for product-type like signals (e.g. (Signal a, Signal b))

rP :: Clock domain gated -> Reset domain synchronous
   -> (Signal domain Int, Signal domain Int)
   -> (Signal domain Int, Signal domain Int)
rP clk rst = registerB clk rst (8,8)

>>> simulateB (rP systemClockGen systemResetGen) [(1,1),(2,2),(3,3)] :: [(Int,Int)]
[(8,8),(1,1),(2,2),(3,3)...
...

Synchronizer circuits for safe clock domain crossings

dualFlipFlopSynchronizer Source #

Arguments

:: Clock domain1 gated1	`Clock` to which the incoming data is synchronised
-> Clock domain2 gated2	`Clock` to which the outgoing data is synchronised
-> Reset domain2 synchronous	`Reset` for registers on the outgoing domain
-> a	Initial value of the two synchronisation registers
-> Signal domain1 a	Incoming data
-> Signal domain2 a	Outgoing, synchronised, data

Synchroniser based on two sequentially connected flip-flops.

NB: This synchroniser can be used for bit-synchronization.
NB: Although this synchroniser does reduce metastability, it does not guarantee the proper synchronisation of a whole word. For example, given that the output is sampled twice as fast as the input is running, and we have two samples in the input stream that look like:
```
[0111,1000]
```
But the circuit driving the input stream has a longer propagation delay on msb compared to the lsbs. What can happen is an output stream that looks like this:
```
[0111,0111,0000,1000]
```
Where the level-change of the msb was not captured, but the level change of the lsbs were.
If you want to have safe word-synchronisation use asyncFIFOSynchronizer.

asyncFIFOSynchronizer Source #

Arguments

:: 2 <= addrSize
=> SNat addrSize	Size of the internally used addresses, the FIFO contains `2^addrSize` elements.
-> Clock wdomain wgated	`Clock` to which the write port is synchronised
-> Clock rdomain rgated	`Clock` to which the read port is synchronised
-> Reset wdomain synchronous
-> Reset rdomain synchronous
-> Signal rdomain Bool	Read request
-> Signal wdomain (Maybe a)	Element to insert
-> (Signal rdomain a, Signal rdomain Bool, Signal wdomain Bool)	(Oldest element in the FIFO, `empty` flag, `full` flag)

Synchroniser implemented as a FIFO around an asynchronous RAM. Based on the design described in Clash.Tutorial, which is itself based on the design described in http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf.

NB: This synchroniser can be used for word-synchronization.

ROMs

asyncRom Source #

Arguments

:: (KnownNat n, Enum addr)
=> Vec n a	ROM content NB: must be a constant
-> addr	Read address `rd`
-> a	The value of the ROM at address `rd`

An asynchronous/combinational ROM with space for n elements

Additional helpful information:

See Clash.Sized.Fixed and Clash.Prelude.BlockRam for ideas on how to use ROMs and RAMs

asyncRomPow2 Source #

Arguments

:: KnownNat n
=> Vec (2 ^ n) a	ROM content NB: must be a constant
-> Unsigned n	Read address `rd`
-> a	The value of the ROM at address `rd`

An asynchronous/combinational ROM with space for 2^n elements

Additional helpful information:

See Clash.Sized.Fixed and Clash.Prelude.BlockRam for ideas on how to use ROMs and RAMs

rom Source #

Arguments

:: (KnownNat n, Enum addr)
=> Clock domain gated	`Clock` to synchronize to
-> Vec n a	ROM content NB: must be a constant
-> Signal domain addr	Read address `rd`
-> Signal domain a	The value of the ROM at address `rd` from the previous clock cycle

A ROM with a synchronous read port, with space for n elements

NB: Read value is delayed by 1 cycle
NB: Initial output value is undefined

Additional helpful information:

See Clash.Sized.Fixed and Clash.Explicit.BlockRam for ideas on how to use ROMs and RAMs

romPow2 Source #

Arguments

:: KnownNat n
=> Clock domain gated	`Clock` to synchronize to
-> Vec (2 ^ n) a	ROM content NB: must be a constant
-> Signal domain (Unsigned n)	Read address `rd`
-> Signal domain a	The value of the ROM at address `rd`

A ROM with a synchronous read port, with space for 2^n elements

NB: Read value is delayed by 1 cycle
NB: Initial output value is undefined

Additional helpful information:

See Clash.Sized.Fixed and Clash.Explicit.BlockRam for ideas on how to use ROMs and RAMs

ROMs initialised with a data file

asyncRomFile Source #

Arguments

:: (KnownNat m, Enum addr)
=> SNat n	Size of the ROM
-> FilePath	File describing the content of the ROM
-> addr	Read address `rd`
-> BitVector m	The value of the ROM at address `rd`

An asynchronous/combinational ROM with space for n elements

NB: This function might not work for specific combinations of code-generation backends and hardware targets. Please check the support table below:

               | VHDL     | Verilog  | SystemVerilog |
===============+==========+==========+===============+
Altera/Quartus | Broken   | Works    | Works         |
Xilinx/ISE     | Works    | Works    | Works         |
ASIC           | Untested | Untested | Untested      |
===============+==========+==========+===============+

Additional helpful information:

See Clash.Prelude.ROM.File for more information on how to instantiate a ROM with the contents of a data file.
See Clash.Sized.Fixed for ideas on how to create your own data files.
When you notice that asyncRomFile is significantly slowing down your simulation, give it a monomorphic type signature. So instead of leaving the type to be inferred:
```
myRomData = asyncRomFile d512 "memory.bin"
```
or giving it a polymorphic type signature:
```
myRomData :: Enum addr => addr -> BitVector 16
myRomData = asyncRomFile d512 "memory.bin"
```
you should give it a monomorphic type signature:
```
myRomData :: Unsigned 9 -> BitVector 16
myRomData = asyncRomFile d512 "memory.bin"
```

asyncRomFilePow2 Source #

Arguments

:: (KnownNat m, KnownNat n)
=> FilePath	File describing the content of the ROM
-> Unsigned n	Read address `rd`
-> BitVector m	The value of the ROM at address `rd`

An asynchronous/combinational ROM with space for 2^n elements

NB: This function might not work for specific combinations of code-generation backends and hardware targets. Please check the support table below:

               | VHDL     | Verilog  | SystemVerilog |
===============+==========+==========+===============+
Altera/Quartus | Broken   | Works    | Works         |
Xilinx/ISE     | Works    | Works    | Works         |
ASIC           | Untested | Untested | Untested      |
===============+==========+==========+===============+

Additional helpful information:

See Clash.Prelude.ROM.File for more information on how to instantiate a ROM with the contents of a data file.
See Clash.Sized.Fixed for ideas on how to create your own data files.
When you notice that asyncRomFilePow2 is significantly slowing down your simulation, give it a monomorphic type signature. So instead of leaving the type to be inferred:
```
myRomData = asyncRomFilePow2 "memory.bin"
```
you should give it a monomorphic type signature:
```
myRomData :: Unsigned 9 -> BitVector 16
myRomData = asyncRomFilePow2 "memory.bin"
```

romFile Source #

Arguments

:: (KnownNat m, Enum addr)
=> Clock domain gated	`Clock` to synchronize to
-> SNat n	Size of the ROM
-> FilePath	File describing the content of the ROM
-> Signal domain addr	Read address `rd`
-> Signal domain (BitVector m)	The value of the ROM at address `rd` from the previous clock cycle

A ROM with a synchronous read port, with space for n elements

NB: Read value is delayed by 1 cycle
NB: Initial output value is undefined

NB: This function might not work for specific combinations of code-generation backends and hardware targets. Please check the support table below:

               | VHDL     | Verilog  | SystemVerilog |
===============+==========+==========+===============+
Altera/Quartus | Broken   | Works    | Works         |
Xilinx/ISE     | Works    | Works    | Works         |
ASIC           | Untested | Untested | Untested      |
===============+==========+==========+===============+

Additional helpful information:

See Clash.Explicit.ROM.File for more information on how to instantiate a ROM with the contents of a data file.
See Clash.Sized.Fixed for ideas on how to create your own data files.

romFilePow2 Source #

Arguments

:: (KnownNat m, KnownNat n)
=> Clock domain gated	`Clock` to synchronize to
-> FilePath	File describing the content of the ROM
-> Signal domain (Unsigned n)	Read address `rd`
-> Signal domain (BitVector m)	The value of the ROM at address `rd` from the previous clock cycle

A ROM with a synchronous read port, with space for 2^n elements

NB: Read value is delayed by 1 cycle
NB: Initial output value is undefined

NB: This function might not work for specific combinations of code-generation backends and hardware targets. Please check the support table below:

               | VHDL     | Verilog  | SystemVerilog |
===============+==========+==========+===============+
Altera/Quartus | Broken   | Works    | Works         |
Xilinx/ISE     | Works    | Works    | Works         |
ASIC           | Untested | Untested | Untested      |
===============+==========+==========+===============+

Additional helpful information:

See Clash.Explicit.ROM.File for more information on how to instantiate a ROM with the contents of a data file.
See Clash.Sized.Fixed for ideas on how to create your own data files.

RAM primitives with a combinational read port

asyncRam Source #

Arguments

:: (Enum addr, HasCallStack)
=> Clock wdom wgated	`Clock` to which to synchronise the write port of the RAM
-> Clock rdom rgated	`Clock` to which the read address signal, `r`, is synchronised
-> SNat n	Size `n` of the RAM
-> Signal rdom addr	Read address `r`
-> Signal wdom (Maybe (addr, a))	(write address `w`, value to write)
-> Signal rdom a	Value of the `RAM` at address `r`

Create a RAM with space for n elements

NB: Initial content of the RAM is undefined

Additional helpful information:

See Clash.Explicit.BlockRam for more information on how to use a RAM.

asyncRamPow2 Source #

Arguments

:: (KnownNat n, HasCallStack)
=> Clock wdom wgated	`Clock` to which to synchronise the write port of the RAM
-> Clock rdom rgated	`Clock` to which the read address signal, `r`, is synchronised
-> Signal rdom (Unsigned n)	Read address `r`
-> Signal wdom (Maybe (Unsigned n, a))	(write address `w`, value to write)
-> Signal rdom a	Value of the `RAM` at address `r`

Create a RAM with space for 2^n elements

NB: Initial content of the RAM is undefined

Additional helpful information:

See Clash.Prelude.BlockRam for more information on how to use a RAM.

BlockRAM primitives

blockRam Source #

Arguments

:: HasCallStack
=> Enum addr
=> Clock dom gated	`Clock` to synchronize to
-> Vec n a	Initial content of the BRAM, also determines the size, `n`, of the BRAM. NB: MUST be a constant.
-> Signal dom addr	Read address `r`
-> Signal dom (Maybe (addr, a))	(write address `w`, value to write)
-> Signal dom a	Value of the `blockRAM` at address `r` from the previous clock cycle

Create a blockRAM with space for n elements

NB: Read value is delayed by 1 cycle
NB: Initial output value is undefined

bram40 :: Clock  domain gated
       -> Signal domain (Unsigned 6)
       -> Signal domain (Maybe (Unsigned 6, Bit))
       -> Signal domain Bit
bram40 clk = blockRam clk (replicate d40 1)

Additional helpful information:

See Clash.Explicit.BlockRam for more information on how to use a Block RAM.
Use the adapter readNew for obtaining write-before-read semantics like this: readNew clk rst (blockRam clk inits) rd wrM.

blockRamPow2 Source #

Arguments

:: (KnownNat n, HasCallStack)
=> Clock dom gated	`Clock` to synchronize to
-> Vec (2 ^ n) a	Initial content of the BRAM, also determines the size, `2^n`, of the BRAM. NB: MUST be a constant.
-> Signal dom (Unsigned n)	Read address `r`
-> Signal dom (Maybe (Unsigned n, a))	(Write address `w`, value to write)
-> Signal dom a	Value of the `blockRAM` at address `r` from the previous clock cycle

Create a blockRAM with space for 2^n elements

NB: Read value is delayed by 1 cycle
NB: Initial output value is undefined

bram32 :: Signal domain (Unsigned 5)
       -> Signal domain (Maybe (Unsigned 5, Bit))
       -> Signal domain Bit
bram32 clk = blockRamPow2 clk (replicate d32 1)

Additional helpful information:

See Clash.Prelude.BlockRam for more information on how to use a Block RAM.
Use the adapter readNew for obtaining write-before-read semantics like this: readNew clk rst (blockRamPow2 clk inits) rd wrM.

BlockRAM primitives initialised with a data file

blockRamFile Source #

Arguments

:: (KnownNat m, Enum addr, HasCallStack)
=> Clock dom gated	`Clock` to synchronize to
-> SNat n	Size of the blockRAM
-> FilePath	File describing the initial content of the blockRAM
-> Signal dom addr	Read address `r`
-> Signal dom (Maybe (addr, BitVector m))	(write address `w`, value to write)
-> Signal dom (BitVector m)	Value of the `blockRAM` at address `r` from the previous clock cycle

Create a blockRAM with space for n elements

NB: Read value is delayed by 1 cycle
NB: Initial output value is undefined

NB: This function might not work for specific combinations of code-generation backends and hardware targets. Please check the support table below:

               | VHDL     | Verilog  | SystemVerilog |
===============+==========+==========+===============+
Altera/Quartus | Broken   | Works    | Works         |
Xilinx/ISE     | Works    | Works    | Works         |
ASIC           | Untested | Untested | Untested      |
===============+==========+==========+===============+

Additional helpful information:

See Clash.Explicit.BlockRam for more information on how to use a Block RAM.
Use the adapter readNew' for obtaining write-before-read semantics like this: readNew' clk (blockRamFile' clk size file) rd wrM.
See Clash.Explicit.BlockRam.File for more information on how to instantiate a Block RAM with the contents of a data file.
See Clash.Sized.Fixed for ideas on how to create your own data files.

blockRamFilePow2 Source #

Arguments

:: (KnownNat m, KnownNat n, HasCallStack)
=> Clock dom gated	`Clock` to synchronize to
-> FilePath	File describing the initial content of the blockRAM
-> Signal dom (Unsigned n)	Read address `r`
-> Signal dom (Maybe (Unsigned n, BitVector m))	(write address `w`, value to write)
-> Signal dom (BitVector m)	Value of the `blockRAM` at address `r` from the previous clock cycle

Create a blockRAM with space for 2^n elements

NB: Read value is delayed by 1 cycle
NB: Initial output value is undefined

NB: This function might not work for specific combinations of code-generation backends and hardware targets. Please check the support table below:

               | VHDL     | Verilog  | SystemVerilog |
===============+==========+==========+===============+
Altera/Quartus | Broken   | Works    | Works         |
Xilinx/ISE     | Works    | Works    | Works         |
ASIC           | Untested | Untested | Untested      |
===============+==========+==========+===============+

Additional helpful information:

See Clash.Prelude.BlockRam for more information on how to use a Block RAM.
Use the adapter readNew' for obtaining write-before-read semantics like this: readNew' clk (blockRamFilePow2' clk file) rd wrM.
See Clash.Explicit.BlockRam.File for more information on how to instantiate a Block RAM with the contents of a data file.
See Clash.Explicit.Fixed for ideas on how to create your own data files.

BlockRAM read/write conflict resolution

readNew Source #

Arguments

:: Eq addr
=> Reset domain synchronous
-> Clock domain gated
-> (Signal domain addr -> Signal domain (Maybe (addr, a)) -> Signal domain a)	The `ram` component
-> Signal domain addr	Read address `r`
-> Signal domain (Maybe (addr, a))	(Write address `w`, value to write)
-> Signal domain a	Value of the `ram` at address `r` from the previous clock cycle

Create read-after-write blockRAM from a read-before-write one

Utility functions

window Source #

Arguments

:: (KnownNat n, Default a)
=> Clock domain gated	Clock to which the incoming signal is synchronized
-> Reset domain synchronous
-> Signal domain a	Signal to create a window over
-> Vec (n + 1) (Signal domain a)	Window of at least size 1

Give a window over a Signal

@ window4

windowD Source #

Arguments

:: (KnownNat n, Default a)
=> Clock domain gated	Clock to which the incoming signal is synchronized
-> Reset domain synchronous
-> Signal domain a	Signal to create a window over
-> Vec (n + 1) (Signal domain a)	Window of at least size 1

Give a delayed window over a Signal

windowD3 :: Clock domain gated -> Reset domain synchronous
         -> Signal domain Int -> Vec 3 (Signal domain Int)
windowD3 = windowD

>>> simulateB (windowD3 systemClockGen systemResetGen) [1::Int,2,3,4] :: [Vec 3 Int]
[<0,0,0>,<1,0,0>,<2,1,0>,<3,2,1>,<4,3,2>...
...

isRising Source #

Arguments

:: (Bounded a, Eq a)
=> Clock domain gated
-> Reset domain synchronous
-> a	Starting value
-> Signal domain a
-> Signal domain Bool

Give a pulse when the Signal goes from minBound to maxBound

isFalling Source #

Arguments

:: (Bounded a, Eq a)
=> Clock domain gated
-> Reset domain synchronous
-> a	Starting value
-> Signal domain a
-> Signal domain Bool

Give a pulse when the Signal goes from maxBound to minBound

Testbench functions

assert Source #

Arguments

:: (Eq a, ShowX a)
=> Clock domain gated
-> Reset domain synchronous
-> String	Additional message
-> Signal domain a	Checked value
-> Signal domain a	Expected value
-> Signal domain b	Return value
-> Signal domain b

Compares the first two Signals for equality and logs a warning when they are not equal. The second Signal is considered the expected value. This function simply returns the third Signal' unaltered as its result. This function is used by outputVerifier.

NB: This function can be used in synthesizable designs.

stimuliGenerator Source #

Arguments

:: KnownNat l
=> Clock domain gated	Clock to which to synchronize the output signal
-> Reset domain synchronous
-> Vec l a	Samples to generate
-> Signal domain a	Signal of given samples

To be used as one of the functions to create the "magical" testInput value, which the CλaSH compiler looks for to create the stimulus generator for the generated VHDL testbench.

Example:

testInput
  :: Clock domain gated -> Reset domain synchronous
  -> Signal domain Int
testInput clk rst = stimuliGenerator clk rst $(listToVecTH [(1::Int),3..21])

>>> sampleN 13 (testInput systemClockGen systemResetGen)
[1,3,5,7,9,11,13,15,17,19,21,21,21]

outputVerifier Source #

Arguments

:: (KnownNat l, Eq a, ShowX a)
=> Clock domain gated	Clock to which the input signal is synchronized to
-> Reset domain synchronous
-> Vec l a	Samples to compare with
-> Signal domain a	Signal to verify
-> Signal domain Bool	Indicator that all samples are verified

To be used as one of the functions to generate the "magical" expectedOutput function, which the CλaSH compiler looks for to create the signal verifier for the generated VHDL testbench.

Example:

expectedOutput
  :: Clock domain gated -> Reset domain synchronous
  -> Signal domain Int -> Signal domain Bool
expectedOutput clk rst = outputVerifier clk rst $(listToVecTH ([70,99,2,3,4,5,7,8,9,10]::[Int]))

>>> import qualified Data.List as List
>>> sampleN 12 (expectedOutput systemClockGen systemResetGen (fromList ([0..10] List.++ [10,10,10])))

cycle(system10000): 0, outputVerifier
expected value: 70, not equal to actual value: 0
[False
cycle(system10000): 1, outputVerifier
expected value: 99, not equal to actual value: 1
,False,False,False,False,False
cycle(system10000): 6, outputVerifier
expected value: 7, not equal to actual value: 6
,False
cycle(system10000): 7, outputVerifier
expected value: 8, not equal to actual value: 7
,False
cycle(system10000): 8, outputVerifier
expected value: 9, not equal to actual value: 8
,False
cycle(system10000): 9, outputVerifier
expected value: 10, not equal to actual value: 9
,False,True,True]

Exported modules

Synchronous signals

module Clash.Explicit.Signal

module Clash.Explicit.Signal.Delayed

DataFlow interface

module Clash.Prelude.DataFlow

Datatypes

Annotations

module Clash.Annotations.TopEntity

Type-level natural numbers

module GHC.TypeLits

module GHC.TypeLits.Extra

module Clash.Promoted.Nat

module Clash.Promoted.Nat.Literals

module Clash.Promoted.Nat.TH

module Clash.Promoted.Symbol

Template Haskell

class Lift t where #

A Lift instance can have any of its values turned into a Template Haskell expression. This is needed when a value used within a Template Haskell quotation is bound outside the Oxford brackets ([| ... |]) but not at the top level. As an example:

add1 :: Int -> Q Exp
add1 x = [| x + 1 |]

Template Haskell has no way of knowing what value x will take on at splice-time, so it requires the type of x to be an instance of Lift.

Lift instances can be derived automatically by use of the -XDeriveLift GHC language extension:

{-# LANGUAGE DeriveLift #-}
module Foo where

import Language.Haskell.TH.Syntax

data Bar a = Bar1 a (Bar a) | Bar2 String
  deriving Lift

Methods

lift :: t -> Q Exp #

Turn a value into a Template Haskell expression, suitable for use in a splice.

Instances

Lift Bool
Methods lift :: Bool -> Q Exp #
Lift Char
Methods lift :: Char -> Q Exp #
Lift Double
Methods lift :: Double -> Q Exp #
Lift Float
Methods lift :: Float -> Q Exp #
Lift Int
Methods lift :: Int -> Q Exp #
Lift Int8
Methods lift :: Int8 -> Q Exp #
Lift Int16
Methods lift :: Int16 -> Q Exp #
Lift Int32
Methods lift :: Int32 -> Q Exp #
Lift Int64
Methods lift :: Int64 -> Q Exp #
Lift Integer
Methods lift :: Integer -> Q Exp #
Lift Natural
Methods lift :: Natural -> Q Exp #
Lift Word
Methods lift :: Word -> Q Exp #
Lift Word8
Methods lift :: Word8 -> Q Exp #
Lift Word16
Methods lift :: Word16 -> Q Exp #
Lift Word32
Methods lift :: Word32 -> Q Exp #
Lift Word64
Methods lift :: Word64 -> Q Exp #
Lift ()
Methods lift :: () -> Q Exp #
Lift Bit #
Methods lift :: Bit -> Q Exp #
Lift a => Lift [a]
Methods lift :: [a] -> Q Exp #
Lift a => Lift (Maybe a)
Methods lift :: Maybe a -> Q Exp #
Integral a => Lift (Ratio a)
Methods lift :: Ratio a -> Q Exp #
KnownNat n => Lift (BitVector n) #
Methods lift :: BitVector n -> Q Exp #
KnownNat n => Lift (Index n) #
Methods lift :: Index n -> Q Exp #
Lift (SNat n) #
Methods lift :: SNat n -> Q Exp #
KnownNat n => Lift (Unsigned n) #
Methods lift :: Unsigned n -> Q Exp #
KnownNat n => Lift (Signed n) #
Methods lift :: Signed n -> Q Exp #
(Lift a, Lift b) => Lift (Either a b)
Methods lift :: Either a b -> Q Exp #
(Lift a, Lift b) => Lift (a, b)
Methods lift :: (a, b) -> Q Exp #
Lift a => Lift (Vec n a) #
Methods lift :: Vec n a -> Q Exp #
Lift a => Lift (Signal domain a) #
Methods lift :: Signal domain a -> Q Exp #
Lift a => Lift (RTree d a) #
Methods lift :: RTree d a -> Q Exp #
(Lift a, Lift b, Lift c) => Lift (a, b, c)
Methods lift :: (a, b, c) -> Q Exp #
(Lift (rep ((+) int frac)), KnownNat frac, KnownNat int, Typeable (Nat -> *) rep) => Lift (Fixed rep int frac) #
Methods lift :: Fixed rep int frac -> Q Exp #
Lift a => Lift (DSignal domain delay a) #
Methods lift :: DSignal domain delay a -> Q Exp #
(Lift a, Lift b, Lift c, Lift d) => Lift (a, b, c, d)
Methods lift :: (a, b, c, d) -> Q Exp #
(Lift a, Lift b, Lift c, Lift d, Lift e) => Lift (a, b, c, d, e)
Methods lift :: (a, b, c, d, e) -> Q Exp #
(Lift a, Lift b, Lift c, Lift d, Lift e, Lift f) => Lift (a, b, c, d, e, f)
Methods lift :: (a, b, c, d, e, f) -> Q Exp #
(Lift a, Lift b, Lift c, Lift d, Lift e, Lift f, Lift g) => Lift (a, b, c, d, e, f, g)
Methods lift :: (a, b, c, d, e, f, g) -> Q Exp #