Portability | non-portable (requires IA-32 processor) |
---|---|
Stability | provisional |
Maintainer | martin@grabmueller.de |
This module provides the function cpuid for accessing the cpuid instruction on modern IA-32 processors. Additionally, some convenience functions are provided, which perform some of the (really complicated and obstruse) decoding.
As an example, you may use the following program to measure the overhead of calling this function:
module Main(main) where import Text.Printf import System.Cpuid main :: IO () main = do (a, b, c, d) <- cpuid 0 printf "basic CPUID usage: EAX=0: %8x %8x %8x %8x\n\n" a b c d vs <- vendorString printf "Vendor string: %s\n\n" vs vs <- brandString printf "Brand string: %s\n\n" vs printf "Cache information:\n" infos <- cacheInfo mapM_ (\ v -> putStrLn $ " " ++ show v) infos putStrLn "" ProcessorInfo{piFamily = fam, piModel = mod, piStepping = step, piType = typ} <- processorInfo printf "processor info: family: %d, model: %d, stepping: %d, processor type: %d\n" fam mod step typ
- data Associativity
- data PageSize
- data Ways = Ways Int
- data Entries = Entries Int
- data CacheSize
- data CacheInfo
- = InstructionTLB (Maybe CacheSize) PageSize Associativity Entries
- | DataTLB (Maybe CacheSize) PageSize Associativity Entries
- | FirstLevelICache CacheSize Associativity LineSize
- | FirstLevelDCache CacheSize Associativity LineSize
- | NoSecondLevelCache
- | SecondLevelCache CacheSize Associativity LineSize (Maybe BytesPerSector)
- | NoThirdLevelCache
- | NoSecondOrThirdLevelCache
- | ThirdLevelCache CacheSize Associativity LineSize (Maybe BytesPerSector)
- | TraceCache MuOps Associativity
- | Prefetching Int
- data LineSize = LineSize Int
- data MuOps = MuOps Int
- data BytesPerSector = BytesPerSector Int
- data ProcessorInfo = ProcessorInfo {}
- cpuid :: Word32 -> IO (Word32, Word32, Word32, Word32)
- processorInfo :: IO ProcessorInfo
- vendorString :: IO String
- brandString :: IO String
- cacheInfo :: IO [CacheInfo]
Data types
data Associativity Source
Cache associativity. For some entries, this is not specified in
the manual. We report these as DirectMapped
.
Page size. Some entries can have alternative page sizes, therefore the complicated type.
Cache size. Some entries can have alternative cache sizes, therefore the complicated type.
Information for caches and TLBs.
InstructionTLB (Maybe CacheSize) PageSize Associativity Entries | Configuration of code TLB. |
DataTLB (Maybe CacheSize) PageSize Associativity Entries | Configuration of data TLB. |
FirstLevelICache CacheSize Associativity LineSize | First-level code cache configuration. |
FirstLevelDCache CacheSize Associativity LineSize | First-level code cache configuration. |
NoSecondLevelCache | No second level support. |
SecondLevelCache CacheSize Associativity LineSize (Maybe BytesPerSector) | Second-level cache configuration. |
NoThirdLevelCache | No third level support. |
NoSecondOrThirdLevelCache | Internal use only. |
ThirdLevelCache CacheSize Associativity LineSize (Maybe BytesPerSector) | Second-level cache configuration. |
TraceCache MuOps Associativity | Trace cache (1st-level code cache) configuration. |
Prefetching Int | Prefetching information. |
Functions
cpuid :: Word32 -> IO (Word32, Word32, Word32, Word32)Source
Execute the cpuid
instructions with the given argument
in the EAX register. Return the values of the registers
EAX, EBX, ECX and EDX in that order.
processorInfo :: IO ProcessorInfoSource
Retrieve basic processor information from the processor using the
cpuid
instruction.
vendorString :: IO StringSource
Execute the cpuid
instruction and return the vendor
string reported by that instruction.
brandString :: IO StringSource
Execute the cpuid
instruction and return the brand string
(processor name and maximum frequency) reported by that
instruction.