cpuid-0.2.1: Binding for the cpuid machine instruction on x86 compatible processors

Portabilitynon-portable (requires IA-32 processor)
Stabilityprovisional
Maintainermartin@grabmueller.de

System.Cpuid

Contents

Description

This module provides the function cpuid for accessing the cpuid instruction on modern IA-32 processors. Additionally, some convenience functions are provided, which perform some of the (really complicated and obstruse) decoding.

As an example, you may use the following program to measure the overhead of calling this function:

 module Main(main) where
 
 import Text.Printf
 import System.Cpuid
 
 main :: IO ()
 main =
     do (a, b, c, d) <- cpuid 0
        printf "basic CPUID usage: EAX=0: %8x %8x %8x %8x\n\n" a b c d
        vs <- vendorString
        printf "Vendor string: %s\n\n" vs
        vs <- brandString
        printf "Brand string: %s\n\n" vs
        printf "Cache information:\n"
        infos <- cacheInfo
        mapM_ (\ v -> putStrLn $ "  " ++ show v) infos
        putStrLn ""
        ProcessorInfo{piFamily = fam, piModel = mod, piStepping = step, piType = typ} <- processorInfo
        printf "processor info: family: %d, model: %d, stepping: %d, processor type: %d\n" fam mod step typ

Synopsis

Data types

data Associativity Source

Cache associativity. For some entries, this is not specified in the manual. We report these as DirectMapped.

Instances

data PageSize Source

Page size. Some entries can have alternative page sizes, therefore the complicated type.

Instances

data Ways Source

Associativity in a set-associative cache.

Constructors

Ways Int 

Instances

data Entries Source

Number of entries in a TLB.

Constructors

Entries Int 

Instances

data CacheSize Source

Cache size. Some entries can have alternative cache sizes, therefore the complicated type.

Instances

data CacheInfo Source

Information for caches and TLBs.

Constructors

InstructionTLB (Maybe CacheSize) PageSize Associativity Entries

Configuration of code TLB.

DataTLB (Maybe CacheSize) PageSize Associativity Entries

Configuration of data TLB.

FirstLevelICache CacheSize Associativity LineSize

First-level code cache configuration.

FirstLevelDCache CacheSize Associativity LineSize

First-level code cache configuration.

NoSecondLevelCache

No second level support.

SecondLevelCache CacheSize Associativity LineSize (Maybe BytesPerSector)

Second-level cache configuration.

NoThirdLevelCache

No third level support.

NoSecondOrThirdLevelCache

Internal use only.

ThirdLevelCache CacheSize Associativity LineSize (Maybe BytesPerSector)

Second-level cache configuration.

TraceCache MuOps Associativity

Trace cache (1st-level code cache) configuration.

Prefetching Int

Prefetching information.

Instances

data LineSize Source

Line size in a cache.

Constructors

LineSize Int 

Instances

data MuOps Source

MuOps in a processors trace cache.

Constructors

MuOps Int 

Instances

data BytesPerSector Source

Bytes per sector in a cache.

Constructors

BytesPerSector Int 

Instances

data ProcessorInfo Source

Processor information.

Constructors

ProcessorInfo 

Fields

piFamily :: Int

Processor family.

piModel :: Int

Processor model.

piStepping :: Int

Processor stepping.

piType :: Int
 

Functions

cpuid :: Word32 -> IO (Word32, Word32, Word32, Word32)Source

Execute the cpuid instructions with the given argument in the EAX register. Return the values of the registers EAX, EBX, ECX and EDX in that order.

processorInfo :: IO ProcessorInfoSource

Retrieve basic processor information from the processor using the cpuid instruction.

vendorString :: IO StringSource

Execute the cpuid instruction and return the vendor string reported by that instruction.

brandString :: IO StringSource

Execute the cpuid instruction and return the brand string (processor name and maximum frequency) reported by that instruction.

cacheInfo :: IO [CacheInfo]Source

Fetch all available cache information from the processor, using the cpuid instruction. The list is not ordered.