Portability	non-portable (requires IA-32 processor)
Stability	provisional
Maintainer	martin@grabmueller.de
Safe Haskell	Safe-Infered

System.Cpuid

Contents

Functions
Data types
Features

Description

This module provides the function cpuid for accessing the cpuid instruction on modern IA-32 processors. Additionally, some convenience functions are provided, which perform some of the (really complicated and obstruse) decoding.

As an example, you may use the following program to determine some characteristics of your machine:

 module Main(main) where

 import Text.Printf (printf, )
 import System.Cpuid

 main :: IO ()
 main = do
    (a, b, c, d) <- cpuid 0
    _ <- printf "Basic CPUID usage: EAX=0: %8x %8x %8x %8x\n\n" a b c d
    _ <- printf "Vendor string: %s\n\n" =<< vendorString
    _ <- printf "Brand string: %s\n\n" =<< brandString
    putStrLn "Cache information:"
    putStrLn . unlines .
       map (\ v -> "  " ++ show v) =<< cacheInfo
    p <- processorInfo
    _ <- printf "Processor info: family: %d, model: %d, stepping: %d, processor type: %d\n"
       (piFamily p) (piModel p) (piStepping p) (piType p)
    return ()

Synopsis

Functions

cpuid :: Word32 -> IO (Word32, Word32, Word32, Word32)Source

Execute the cpuid instructions with the given argument in the EAX register. Return the values of the registers EAX, EBX, ECX and EDX in that order.

processorInfo :: IO ProcessorInfo Source

Retrieve basic processor information from the processor using the cpuid instruction.

vendorString :: IO String Source

Execute the cpuid instruction and return the vendor string reported by that instruction.

brandString :: IO String Source

Execute the cpuid instruction and return the brand string (processor name and maximum frequency) reported by that instruction.

cacheInfo :: IO [CacheInfo]Source

Fetch all available cache information from the processor, using the cpuid instruction. The list is not ordered.

Data types

data Associativity Source

Cache associativity. For some entries, this is not specified in the manual. We report these as DirectMapped.

Constructors

SetAssociative Ways
DirectMapped

Instances

Show Associativity

data PageSize Source

Page size. Some entries can have alternative page sizes, therefore the complicated type.

Constructors

PageSize Int
PageSizeOr PageSize PageSize

Instances

Show PageSize

newtype Ways Source

Associativity in a set-associative cache.

Constructors

Ways Int

Instances

Show Ways

newtype Entries Source

Number of entries in a TLB.

Constructors

Entries Int

Instances

Show Entries

data CacheSize Source

Cache size. Some entries can have alternative cache sizes, therefore the complicated type.

Constructors

CacheSize Int
CacheSizeOr CacheSize CacheSize

Instances

Show CacheSize

data CacheInfo Source

Information for caches and TLBs.

Constructors

InstructionTLB (Maybe CacheSize) PageSize Associativity Entries	Configuration of code TLB.
DataTLB (Maybe CacheSize) PageSize Associativity Entries	Configuration of data TLB.
FirstLevelICache CacheSize Associativity LineSize	First-level code cache configuration.
FirstLevelDCache CacheSize Associativity LineSize	First-level code cache configuration.
NoSecondLevelCache	No second level support.
SecondLevelCache CacheSize Associativity LineSize (Maybe BytesPerSector)	Second-level cache configuration.
NoThirdLevelCache	No third level support.
NoSecondOrThirdLevelCache	Internal use only.
ThirdLevelCache CacheSize Associativity LineSize (Maybe BytesPerSector)	Second-level cache configuration.
TraceCache MuOps Associativity	Trace cache (1st-level code cache) configuration.
Prefetching Int	Prefetching information.