Safe Haskell | None |
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Language | GHC2021 |
Put common type definitions here to break recursive module dependencies.
Synopsis
- data BlockAssignment freeRegs
- lookupBlockAssignment :: BlockId -> BlockAssignment freeRegs -> Maybe (freeRegs, RegMap Loc)
- lookupFirstUsed :: VirtualReg -> BlockAssignment freeRegs -> Maybe RealReg
- emptyBlockAssignment :: BlockAssignment freeRegs
- updateBlockAssignment :: BlockId -> (freeRegs, RegMap Loc) -> BlockAssignment freeRegs -> BlockAssignment freeRegs
- data Loc
- regsOfLoc :: Loc -> [RealReg]
- data SpillReason
- data RegAllocStats = RegAllocStats {
- ra_spillInstrs :: UniqFM Unique [Int]
- ra_fixupList :: [(BlockId, BlockId, BlockId)]
- data RA_State freeRegs = RA_State {
- ra_blockassig :: BlockAssignment freeRegs
- ra_freeregs :: !freeRegs
- ra_assig :: RegMap Loc
- ra_delta :: Int
- ra_stack :: StackMap
- ra_us :: UniqSupply
- ra_spills :: [SpillReason]
- ra_config :: !NCGConfig
- ra_fixups :: [(BlockId, BlockId, BlockId)]
Documentation
data BlockAssignment freeRegs Source #
Used to store the register assignment on entry to a basic block. We use this to handle join points, where multiple branch instructions target a particular label. We have to insert fixup code to make the register assignments from the different sources match up.
lookupBlockAssignment :: BlockId -> BlockAssignment freeRegs -> Maybe (freeRegs, RegMap Loc) Source #
Find the register mapping for a specific BlockId.
lookupFirstUsed :: VirtualReg -> BlockAssignment freeRegs -> Maybe RealReg Source #
Lookup which register a virtual register was first assigned to.
emptyBlockAssignment :: BlockAssignment freeRegs Source #
An initial empty BlockAssignment
updateBlockAssignment :: BlockId -> (freeRegs, RegMap Loc) -> BlockAssignment freeRegs -> BlockAssignment freeRegs Source #
Add new register mappings for a specific block.
Where a vreg is currently stored A temporary can be marked as living in both a register and memory (InBoth), for example if it was recently loaded from a spill location. This makes it cheap to spill (no save instruction required), but we have to be careful to turn this into InReg if the value in the register is changed.
InReg !RealReg | vreg is in a register |
InMem !StackSlot | vreg is held in a stack slot |
InBoth !RealReg !StackSlot | vreg is held in both a register and a stack slot |
data SpillReason Source #
Reasons why instructions might be inserted by the spiller. Used when generating stats for -ddrop-asm-stats.
SpillAlloc !Unique | vreg was spilled to a slot so we could use its current hreg for another vreg |
SpillClobber !Unique | vreg was moved because its hreg was clobbered |
SpillLoad !Unique | vreg was loaded from a spill slot |
SpillJoinRR !Unique | reg-reg move inserted during join to targets |
SpillJoinRM !Unique | reg-mem move inserted during join to targets |
data RegAllocStats Source #
Used to carry interesting stats out of the register allocator.
RegAllocStats | |
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data RA_State freeRegs Source #
The register allocator state
RA_State | |
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