GHC.CmmToAsm.AArch64.Instr

Documentation

stackFrameHeaderSize :: Int

LR and FP (8 byte each) are the prologue of each stack frame

spillSlotSize :: Int

All registers are 8 byte wide.

stackAlign :: Int

The number of bytes that the stack pointer should be aligned to.

maxSpillSlots :: NCGConfig -> Int

The number of spill slots available without allocating more.

spillSlotToOffset :: NCGConfig -> Int -> Int

Convert a spill slot number to a *byte* offset, with no sign.

regUsageOfInstr :: Platform -> Instr -> RegUsage

callerSavedRegisters :: [Reg]

0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 42 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | |== General Purpose registers ==================================================================================================================================| | argument passing ------------- | IR | tmp registers -------- | IP0| IP1| PL | callee saved ------------ | FP | LR | SP | | free registers -------------------------------------------------------------------- | BR | Sp | Hp | R1 | R2 | R3 | R4 | R5 | R6 | SL | -- | -- | -- | |== SIMD/FP Registers ==========================================================================================================================================| | argument passing ------------- | callee saved (lower 64 bits) --- | caller saved ---------------------- | | free registers ------------- | F1 | F2 | F3 | F4 | D1 | D2 | D3 | D4 | free registers ----------------------------------------------------- | '---------------------------------------------------------------------------------------------------------------------------------------------------------------' IR: Indirect result location register, IP: Intra-procedure register, PL: Platform register, FP: Frame pointer, LR: Link register, SP: Stack pointer BR: Base, SL: SpLim

patchRegsOfInstr :: Instr -> (Reg -> Reg) -> Instr

Apply a given mapping to all the register references in this instruction.

isJumpishInstr :: Instr -> Bool

Checks whether this instruction is a jump/branch instruction. One that can change the flow of control in a way that the register allocator needs to worry about.

jumpDestsOfInstr :: Instr -> [BlockId]

Checks whether this instruction is a jump/branch instruction. One that can change the flow of control in a way that the register allocator needs to worry about.

patchJumpInstr :: Instr -> (BlockId -> BlockId) -> Instr

Change the destination of this jump instruction. Used in the linear allocator when adding fixup blocks for join points.

mkSpillInstr :: HasCallStack => NCGConfig -> Reg -> Int -> Int -> [Instr]

An instruction to spill a register into a spill slot.

mkLoadInstr :: NCGConfig -> Reg -> Int -> Int -> [Instr]

takeDeltaInstr :: Instr -> Maybe Int

See if this instruction is telling us the current C stack delta

isMetaInstr :: Instr -> Bool

mkRegRegMoveInstr :: Reg -> Reg -> Instr

Copy the value in a register to another one. Must work for all register classes.

takeRegRegMoveInstr :: Instr -> Maybe (Reg, Reg)

Take the source and destination from this reg -> reg move instruction or Nothing if it's not one

mkJumpInstr :: BlockId -> [Instr]

Make an unconditional jump instruction.

mkStackAllocInstr :: Platform -> Int -> [Instr]

mkStackDeallocInstr :: Platform -> Int -> [Instr]

allocMoreStack :: Platform -> Int -> NatCmmDecl statics Instr -> UniqSM (NatCmmDecl statics Instr, [(BlockId, BlockId)])

data Instr

Constructors

COMMENT SDoc

MULTILINE_COMMENT SDoc

ANN SDoc Instr

LOCATION Int Int Int String

NEWBLOCK BlockId

DELTA Int

SXTB Operand Operand

UXTB Operand Operand

SXTH Operand Operand

UXTH Operand Operand

PUSH_STACK_FRAME

SXTW Operand Operand | SXTX Operand Operand

POP_STACK_FRAME

ADD Operand Operand Operand

ADC Operand Operand Operand -- rd = rn + rm + C | ADCS ...

CMP Operand Operand

ADDS Operand Operand Operand -- rd = rn + rm | ADR ... | ADRP ...

MSUB Operand Operand Operand Operand

MADD ... | MNEG ...

MUL Operand Operand Operand

NEG Operand Operand

SDIV Operand Operand Operand

NEGS ... | NGC ... | NGCS ... | SBC ... | SBCS ...

SMULH Operand Operand Operand

SMADDL ... | SMNEGL ... | SMSUBL ...

SMULL Operand Operand Operand

SUB Operand Operand Operand

UDIV Operand Operand Operand

SUBS ...

SBFM Operand Operand Operand Operand

UMADDL ... -- Xd = Xa + Wn × Wm | UMNEGL ... -- Xd = - Wn × Wm | UMSUBL ... -- Xd = Xa - Wn × Wm | UMULH ... -- Xd = (Xn × Xm)_127:64 | UMULL ... -- Xd = Wn × Wm

UBFM Operand Operand Operand Operand

SBFX Operand Operand Operand Operand

UBFX Operand Operand Operand Operand

AND Operand Operand Operand

ASR Operand Operand Operand

EOR Operand Operand Operand

LSL Operand Operand Operand

LSR Operand Operand Operand

MOV Operand Operand

MOVK Operand Operand

MOVZ Operand Operand

MOVN Operand Operand

MVN Operand Operand

ORR Operand Operand Operand

STR Format Operand Operand

STLR Format Operand Operand

LDR Format Operand Operand

LDAR Format Operand Operand

CSET Operand Cond

CBZ Operand Target

CBNZ Operand Target

J Target

B Target

BL Target [Reg] [Reg]

BCOND Cond Target

DMBISH

FCVT Operand Operand

SCVTF Operand Operand

FCVTZS Operand Operand

FABS Operand Operand

FMA FMASign Operand Operand Operand Operand

Floating-point fused multiply-add instructions

• fmadd : d = r1 * r2 + r3
• fnmsub: d = r1 * r2 - r3
• fmsub : d = - r1 * r2 + r3
• fnmadd: d = - r1 * r2 - r3

Instances

Instruction Instr

Instruction instance for aarch64

Defined in GHC.CmmToAsm.AArch64

Methods

regUsageOfInstr :: Platform -> Instr -> RegUsage

patchRegsOfInstr :: Instr -> (Reg -> Reg) -> Instr

isJumpishInstr :: Instr -> Bool

jumpDestsOfInstr :: Instr -> [BlockId]

patchJumpInstr :: Instr -> (BlockId -> BlockId) -> Instr

mkSpillInstr :: NCGConfig -> Reg -> Int -> Int -> [Instr]

mkLoadInstr :: NCGConfig -> Reg -> Int -> Int -> [Instr]

takeDeltaInstr :: Instr -> Maybe Int

isMetaInstr :: Instr -> Bool

mkRegRegMoveInstr :: Platform -> Reg -> Reg -> Instr

takeRegRegMoveInstr :: Instr -> Maybe (Reg, Reg)

mkJumpInstr :: BlockId -> [Instr]

mkStackAllocInstr :: Platform -> Int -> [Instr]

mkStackDeallocInstr :: Platform -> Int -> [Instr]

pprInstr :: Platform -> Instr -> SDoc

mkComment :: FastString -> [Instr]

instrCon :: Instr -> String

data Target

Constructors

TBlock BlockId

TLabel CLabel

TReg Reg

Instances

Eq Target

Defined in GHC.CmmToAsm.AArch64.Instr

Methods

(==) :: Target -> Target -> Bool

(/=) :: Target -> Target -> Bool

Ord Target

Defined in GHC.CmmToAsm.AArch64.Instr

Methods

compare :: Target -> Target -> Ordering

(<) :: Target -> Target -> Bool

(<=) :: Target -> Target -> Bool

(>) :: Target -> Target -> Bool

(>=) :: Target -> Target -> Bool

max :: Target -> Target -> Target

min :: Target -> Target -> Target

data ExtMode

Constructors

EUXTB

EUXTH

EUXTW

EUXTX

ESXTB

ESXTH

ESXTW

ESXTX

Instances

Show ExtMode

Defined in GHC.CmmToAsm.AArch64.Instr

Methods

showsPrec :: Int -> ExtMode -> ShowS

show :: ExtMode -> String

showList :: [ExtMode] -> ShowS

Eq ExtMode

Defined in GHC.CmmToAsm.AArch64.Instr

Methods

(==) :: ExtMode -> ExtMode -> Bool

(/=) :: ExtMode -> ExtMode -> Bool

data ShiftMode

Constructors

SLSL

SLSR

SASR

SROR

Instances

Show ShiftMode

Defined in GHC.CmmToAsm.AArch64.Instr

Methods

showsPrec :: Int -> ShiftMode -> ShowS

show :: ShiftMode -> String

showList :: [ShiftMode] -> ShowS

Eq ShiftMode

Defined in GHC.CmmToAsm.AArch64.Instr

Methods

(==) :: ShiftMode -> ShiftMode -> Bool

(/=) :: ShiftMode -> ShiftMode -> Bool

type ExtShift = Int

type RegShift = Int

data Operand

Constructors

OpReg Width Reg

OpRegExt Width Reg ExtMode ExtShift

OpRegShift Width Reg ShiftMode RegShift

OpImm Imm

OpImmShift Imm ShiftMode RegShift

OpAddr AddrMode

Instances

Show Operand

Defined in GHC.CmmToAsm.AArch64.Instr

Methods

showsPrec :: Int -> Operand -> ShowS

show :: Operand -> String

showList :: [Operand] -> ShowS

Eq Operand

Defined in GHC.CmmToAsm.AArch64.Instr

Methods

(==) :: Operand -> Operand -> Bool

(/=) :: Operand -> Operand -> Bool

opReg :: Width -> Reg -> Operand

xzr :: Operand

wzr :: Operand

sp :: Operand

ip0 :: Operand

reg_zero :: Reg

_x :: Int -> Operand

x0 :: Operand

x1 :: Operand

x2 :: Operand

x3 :: Operand

x4 :: Operand

x5 :: Operand

x6 :: Operand

x7 :: Operand

x8 :: Operand

x9 :: Operand

x10 :: Operand

x11 :: Operand

x12 :: Operand

x13 :: Operand

x14 :: Operand

x15 :: Operand

x16 :: Operand

x17 :: Operand

x18 :: Operand

x19 :: Operand

x20 :: Operand

x21 :: Operand

x22 :: Operand

x23 :: Operand

x24 :: Operand

x25 :: Operand

x26 :: Operand

x27 :: Operand

x28 :: Operand

x29 :: Operand

x30 :: Operand

x31 :: Operand

_d :: Int -> Operand

d0 :: Operand

d1 :: Operand

d2 :: Operand

d3 :: Operand

d4 :: Operand

d5 :: Operand

d6 :: Operand

d7 :: Operand

d8 :: Operand

d9 :: Operand

d10 :: Operand

d11 :: Operand

d12 :: Operand

d13 :: Operand

d14 :: Operand

d15 :: Operand

d16 :: Operand

d17 :: Operand

d18 :: Operand

d19 :: Operand

d20 :: Operand

d21 :: Operand

d22 :: Operand

d23 :: Operand

d24 :: Operand

d25 :: Operand

d26 :: Operand

d27 :: Operand

d28 :: Operand

d29 :: Operand

d30 :: Operand

d31 :: Operand

opRegUExt :: Width -> Reg -> Operand

opRegSExt :: Width -> Reg -> Operand

Orphan instances

Outputable RegUsage

Get the registers that are being used by this instruction. regUsage doesn't need to do any trickery for jumps and such. Just state precisely the regs read and written by that insn. The consequences of control flow transfers, as far as register allocation goes, are taken care of by the register allocator.

RegUsage = RU [regs] [regs]

Methods

ppr :: RegUsage -> SDoc