Copyright	(c) Inokentiy Babushkin, 2016
License	BSD3
Maintainer	Inokentiy Babushkin <inokentiy.babushkin@googlemail.com>
Stability	experimental
Safe Haskell	Safe
Language	Haskell2010

Hapstone.Internal.Arm

Description

This module contains ARM specific datatypes and their respective Storable instances. Most of the types are used internally and can be looked up here. Some of them are currently unused, as the headers only define them as symbolic constants whose type is never used explicitly, which poses a problem for a memory-safe port to the Haskell language, this is about to get fixed in a future version.

Apart from that, because the module is generated using C2HS, some of the documentation is misplaced or rendered incorrectly, so if in doubt, read the source file.

Synopsis

Documentation

data ArmShifter Source

ARM shift type

Constructors

ArmSftInvalid
ArmSftAsr
ArmSftLsl
ArmSftLsr
ArmSftRor
ArmSftRrx
ArmSftAsrReg
ArmSftLslReg
ArmSftLsrReg
ArmSftRorReg
ArmSftRrxReg

Instances

Bounded ArmShifter Source
Enum ArmShifter Source
Eq ArmShifter Source
Show ArmShifter Source

data ArmConditionCode Source

ARM condition code

Constructors

ArmCcInvalid
ArmCcEq
ArmCcNe
ArmCcHs
ArmCcLo
ArmCcMi
ArmCcPl
ArmCcVs
ArmCcVc
ArmCcHi
ArmCcLs
ArmCcGe
ArmCcLt
ArmCcGt
ArmCcLe
ArmCcAl

Instances

Bounded ArmConditionCode Source
Enum ArmConditionCode Source
Eq ArmConditionCode Source
Show ArmConditionCode Source

data ArmMemBarrier Source

memory barrier operands (map directly to the 4-bit encoding of the option field for Memory Barrier operations, when given as an integer)

Constructors

ArmMbInvalid
ArmMbReserved0
ArmMbOshld
ArmMbOshst
ArmMbOsh
ArmMbReserved4
ArmMbNshld
ArmMbNshst
ArmMbNsh
ArmMbReserved8
ArmMbIshld
ArmMbIshst
ArmMbIsh
ArmMbReserved12
ArmMbLd
ArmMbSt
ArmMbSy

Instances

Bounded ArmMemBarrier Source
Enum ArmMemBarrier Source
Eq ArmMemBarrier Source
Show ArmMemBarrier Source

data ArmOpType Source

operand type for instruction's operands

Constructors

ArmOpInvalid
ArmOpReg
ArmOpImm
ArmOpMem
ArmOpFp
ArmOpCimm
ArmOpPimm
ArmOpSetend
ArmOpSysreg

Instances

Bounded ArmOpType Source
Enum ArmOpType Source
Eq ArmOpType Source
Show ArmOpType Source

data ArmSetendType Source

operand type for SETEND instruction

Constructors

ArmSetendInvalid
ArmSetendBe
ArmSetendLe

Instances

Bounded ArmSetendType Source
Enum ArmSetendType Source	operand type for SETEND instruction
Eq ArmSetendType Source
Show ArmSetendType Source

data ArmCpsmodeType Source

Constructors

ArmCpsmodeInvalid
ArmCpsmodeIe
ArmCpsmodeId

Instances

Bounded ArmCpsmodeType Source
Enum ArmCpsmodeType Source
Eq ArmCpsmodeType Source
Show ArmCpsmodeType Source

data ArmCpsflagType Source

Constructors

ArmCpsflagInvalid
ArmCpsflagF
ArmCpsflagI
ArmCpsflagA
ArmCpsflagNone

Instances

Bounded ArmCpsflagType Source
Enum ArmCpsflagType Source	memory access operands associated with `ArmOpMem` operand type
Eq ArmCpsflagType Source
Show ArmCpsflagType Source

data ArmVectordataType Source

data type for elements of vector instructions

Instances

Bounded ArmVectordataType Source
Enum ArmVectordataType Source
Eq ArmVectordataType Source
Show ArmVectordataType Source

data ArmOpMemStruct Source

Constructors

ArmOpMemStruct
Fields base :: Word32 base register index :: Word32 index register scale :: Int32 scale for index register (1 or -1) disp :: Int32 displacement/offset value

Instances

Eq ArmOpMemStruct Source
Show ArmOpMemStruct Source
Storable ArmOpMemStruct Source

data CsArmOpValue Source

possible operand types (corresponding to the tagged union in the C header)

Constructors

Reg Word32	register value for `ArmOpReg` operands
Sysreg Word32	register value for `ArmOpSysreg` operands
Imm Int32	immediate value for `ArmOpImm` operands
Cimm Int32	immediate value for `ArmOpCimm` operands
Pimm Int32	immediate value for `ArmOpPimm` operands
Fp Double	floating point value for `ArmOpFp` operands
Mem ArmOpMemStruct	base,index,scale,disp value for `ArmOpMem` operands
Setend ArmSetendType	SETEND instruction's operand type
Undefined	invalid operand value, for `ArmOpInvalid` operand

Instances

Eq CsArmOpValue Source
Show CsArmOpValue Source

data CsArmOp Source

instruction operands

Constructors

CsArmOp
Fields vectorIndex :: Int32 vector index for some vector operands, else -1 shift :: (ArmShifter, Word32) shifter type and value value :: CsArmOpValue operand type and value subtracted :: Bool if `True`, operand is subtracted, else added

Instances

Eq CsArmOp Source
Show CsArmOp Source
Storable CsArmOp Source

data CsArm Source

instruction datatype

Constructors

CsArm

Fields

usermode :: Bool: usermode registers to be loaded (for LDM/STM instructions)
vectorSize :: Int32: scalar size for vector instructions
vectorData :: ArmVectordataType: data type for elements of vector instructions
cpsMode :: ArmCpsmodeType: CPS mode for CPS instructions
cpsFlag :: ArmCpsflagType: CPS mode for CPS instructions
cc :: ArmConditionCode
updateFlags :: Bool
writeback :: Bool: does this instruction request writeback?
memBarrier :: ArmMemBarrier: options for some memory barrier instructions
operands :: [CsArmOp]: operand list of this instruction, *MUST* have <= 36 elements, else you'll get a runtime error when you (implicitly) try to write it to memory via it's Storable instance

Instances

Eq CsArm Source
Show CsArm Source
Storable CsArm Source

data ArmReg Source

ARM registers

Constructors

ArmRegInvalid
ArmRegApsr
ArmRegApsrNzcv
ArmRegCpsr
ArmRegFpexc
ArmRegFpinst
ArmRegFpscr
ArmRegFpscrNzcv
ArmRegFpsid
ArmRegItstate
ArmRegLr
ArmRegR14
ArmRegPc
ArmRegR15
ArmRegSp
ArmRegR13
ArmRegSpsr
ArmRegD0
ArmRegD1
ArmRegD2
ArmRegD3
ArmRegD4
ArmRegD5
ArmRegD6
ArmRegD7
ArmRegD8
ArmRegD9
ArmRegD10
ArmRegD11
ArmRegD12
ArmRegD13
ArmRegD14
ArmRegD15
ArmRegD16
ArmRegD17
ArmRegD18
ArmRegD19
ArmRegD20
ArmRegD21
ArmRegD22
ArmRegD23
ArmRegD24
ArmRegD25
ArmRegD26
ArmRegD27
ArmRegD28
ArmRegD29
ArmRegD30
ArmRegD31
ArmRegFpinst2
ArmRegMvfr0
ArmRegMvfr1
ArmRegMvfr2
ArmRegQ0
ArmRegQ1
ArmRegQ2
ArmRegQ3
ArmRegQ4
ArmRegQ5
ArmRegQ6
ArmRegQ7
ArmRegQ8
ArmRegQ9
ArmRegQ10
ArmRegQ11
ArmRegQ12
ArmRegQ13
ArmRegQ14
ArmRegQ15
ArmRegR0
ArmRegR1
ArmRegR2
ArmRegR3
ArmRegR4
ArmRegR5
ArmRegR6
ArmRegR7
ArmRegR8
ArmRegR9
ArmRegSb
ArmRegR10
ArmRegSl
ArmRegR11
ArmRegFp
ArmRegR12
ArmRegIp
ArmRegS0
ArmRegS1
ArmRegS2
ArmRegS3
ArmRegS4
ArmRegS5
ArmRegS6
ArmRegS7
ArmRegS8
ArmRegS9
ArmRegS10
ArmRegS11
ArmRegS12
ArmRegS13
ArmRegS14
ArmRegS15
ArmRegS16
ArmRegS17
ArmRegS18
ArmRegS19
ArmRegS20
ArmRegS21
ArmRegS22
ArmRegS23
ArmRegS24
ArmRegS25
ArmRegS26
ArmRegS27
ArmRegS28
ArmRegS29
ArmRegS30
ArmRegS31
ArmRegEnding

Instances

Bounded ArmReg Source
Enum ArmReg Source
Eq ArmReg Source
Show ArmReg Source

data ArmInsn Source

ARM instructions

Constructors

ArmInsInvalid
ArmInsAdc
ArmInsAdd
ArmInsAdr
ArmInsAesd
ArmInsAese
ArmInsAesimc
ArmInsAesmc
ArmInsAnd
ArmInsBfc
ArmInsBfi
ArmInsBic
ArmInsBkpt
ArmInsBl
ArmInsBlx
ArmInsBx
ArmInsBxj
ArmInsB
ArmInsCdp
ArmInsCdp2
ArmInsClrex
ArmInsClz
ArmInsCmn
ArmInsCmp
ArmInsCps
ArmInsCrc32b
ArmInsCrc32cb
ArmInsCrc32ch
ArmInsCrc32cw
ArmInsCrc32h
ArmInsCrc32w
ArmInsDbg
ArmInsDmb
ArmInsDsb
ArmInsEor
ArmInsVmov
ArmInsFldmdbx
ArmInsFldmiax
ArmInsVmrs
ArmInsFstmdbx
ArmInsFstmiax
ArmInsHint
ArmInsHlt
ArmInsIsb
ArmInsLda
ArmInsLdab
ArmInsLdaex
ArmInsLdaexb
ArmInsLdaexd
ArmInsLdaexh
ArmInsLdah
ArmInsLdc2l
ArmInsLdc2
ArmInsLdcl
ArmInsLdc
ArmInsLdmda
ArmInsLdmdb
ArmInsLdm
ArmInsLdmib
ArmInsLdrbt
ArmInsLdrb
ArmInsLdrd
ArmInsLdrex
ArmInsLdrexb
ArmInsLdrexd
ArmInsLdrexh
ArmInsLdrh
ArmInsLdrht
ArmInsLdrsb
ArmInsLdrsbt
ArmInsLdrsh
ArmInsLdrsht
ArmInsLdrt
ArmInsLdr
ArmInsMcr
ArmInsMcr2
ArmInsMcrr
ArmInsMcrr2
ArmInsMla
ArmInsMls
ArmInsMov
ArmInsMovt
ArmInsMovw
ArmInsMrc
ArmInsMrc2
ArmInsMrrc
ArmInsMrrc2
ArmInsMrs
ArmInsMsr
ArmInsMul
ArmInsMvn
ArmInsOrr
ArmInsPkhbt
ArmInsPkhtb
ArmInsPldw
ArmInsPld
ArmInsPli
ArmInsQadd
ArmInsQadd16
ArmInsQadd8
ArmInsQasx
ArmInsQdadd
ArmInsQdsub
ArmInsQsax
ArmInsQsub
ArmInsQsub16
ArmInsQsub8
ArmInsRbit
ArmInsRev
ArmInsRev16
ArmInsRevsh
ArmInsRfeda
ArmInsRfedb
ArmInsRfeia
ArmInsRfeib
ArmInsRsb
ArmInsRsc
ArmInsSadd16
ArmInsSadd8
ArmInsSasx
ArmInsSbc
ArmInsSbfx
ArmInsSdiv
ArmInsSel
ArmInsSetend
ArmInsSha1c
ArmInsSha1h
ArmInsSha1m
ArmInsSha1p
ArmInsSha1su0
ArmInsSha1su1
ArmInsSha256h
ArmInsSha256h2
ArmInsSha256su0
ArmInsSha256su1
ArmInsShadd16
ArmInsShadd8
ArmInsShasx
ArmInsShsax
ArmInsShsub16
ArmInsShsub8
ArmInsSmc
ArmInsSmlabb
ArmInsSmlabt
ArmInsSmlad
ArmInsSmladx
ArmInsSmlal
ArmInsSmlalbb
ArmInsSmlalbt
ArmInsSmlald
ArmInsSmlaldx
ArmInsSmlaltb
ArmInsSmlaltt
ArmInsSmlatb
ArmInsSmlatt
ArmInsSmlawb
ArmInsSmlawt
ArmInsSmlsd
ArmInsSmlsdx
ArmInsSmlsld
ArmInsSmlsldx
ArmInsSmmla
ArmInsSmmlar
ArmInsSmmls
ArmInsSmmlsr
ArmInsSmmul
ArmInsSmmulr
ArmInsSmuad
ArmInsSmuadx
ArmInsSmulbb
ArmInsSmulbt
ArmInsSmull
ArmInsSmultb
ArmInsSmultt
ArmInsSmulwb
ArmInsSmulwt
ArmInsSmusd
ArmInsSmusdx
ArmInsSrsda
ArmInsSrsdb
ArmInsSrsia
ArmInsSrsib
ArmInsSsat
ArmInsSsat16
ArmInsSsax
ArmInsSsub16
ArmInsSsub8
ArmInsStc2l
ArmInsStc2
ArmInsStcl
ArmInsStc
ArmInsStl
ArmInsStlb
ArmInsStlex
ArmInsStlexb
ArmInsStlexd
ArmInsStlexh
ArmInsStlh
ArmInsStmda
ArmInsStmdb
ArmInsStm
ArmInsStmib
ArmInsStrbt
ArmInsStrb
ArmInsStrd
ArmInsStrex
ArmInsStrexb
ArmInsStrexd
ArmInsStrexh
ArmInsStrh
ArmInsStrht
ArmInsStrt
ArmInsStr
ArmInsSub
ArmInsSvc
ArmInsSwp
ArmInsSwpb
ArmInsSxtab
ArmInsSxtab16
ArmInsSxtah
ArmInsSxtb
ArmInsSxtb16
ArmInsSxth
ArmInsTeq
ArmInsTrap
ArmInsTst
ArmInsUadd16
ArmInsUadd8
ArmInsUasx
ArmInsUbfx
ArmInsUdf
ArmInsUdiv
ArmInsUhadd16
ArmInsUhadd8
ArmInsUhasx
ArmInsUhsax
ArmInsUhsub16
ArmInsUhsub8
ArmInsUmaal
ArmInsUmlal
ArmInsUmull
ArmInsUqadd16
ArmInsUqadd8
ArmInsUqasx
ArmInsUqsax
ArmInsUqsub16
ArmInsUqsub8
ArmInsUsad8
ArmInsUsada8
ArmInsUsat
ArmInsUsat16
ArmInsUsax
ArmInsUsub16
ArmInsUsub8
ArmInsUxtab
ArmInsUxtab16
ArmInsUxtah
ArmInsUxtb
ArmInsUxtb16
ArmInsUxth
ArmInsVabal
ArmInsVaba
ArmInsVabdl
ArmInsVabd
ArmInsVabs
ArmInsVacge
ArmInsVacgt
ArmInsVadd
ArmInsVaddhn
ArmInsVaddl
ArmInsVaddw
ArmInsVand
ArmInsVbic
ArmInsVbif
ArmInsVbit
ArmInsVbsl
ArmInsVceq
ArmInsVcge
ArmInsVcgt
ArmInsVcle
ArmInsVcls
ArmInsVclt
ArmInsVclz
ArmInsVcmp
ArmInsVcmpe
ArmInsVcnt
ArmInsVcvta
ArmInsVcvtb
ArmInsVcvt
ArmInsVcvtm
ArmInsVcvtn
ArmInsVcvtp
ArmInsVcvtt
ArmInsVdiv
ArmInsVdup
ArmInsVeor
ArmInsVext
ArmInsVfma
ArmInsVfms
ArmInsVfnma
ArmInsVfnms
ArmInsVhadd
ArmInsVhsub
ArmInsVld1
ArmInsVld2
ArmInsVld3
ArmInsVld4
ArmInsVldmdb
ArmInsVldmia
ArmInsVldr
ArmInsVmaxnm
ArmInsVmax
ArmInsVminnm
ArmInsVmin
ArmInsVmla
ArmInsVmlal
ArmInsVmls
ArmInsVmlsl
ArmInsVmovl
ArmInsVmovn
ArmInsVmsr
ArmInsVmul
ArmInsVmull
ArmInsVmvn
ArmInsVneg
ArmInsVnmla
ArmInsVnmls
ArmInsVnmul
ArmInsVorn
ArmInsVorr
ArmInsVpadal
ArmInsVpaddl
ArmInsVpadd
ArmInsVpmax
ArmInsVpmin
ArmInsVqabs
ArmInsVqadd
ArmInsVqdmlal
ArmInsVqdmlsl
ArmInsVqdmulh
ArmInsVqdmull
ArmInsVqmovun
ArmInsVqmovn
ArmInsVqneg
ArmInsVqrdmulh
ArmInsVqrshl
ArmInsVqrshrn
ArmInsVqrshrun
ArmInsVqshl
ArmInsVqshlu
ArmInsVqshrn
ArmInsVqshrun
ArmInsVqsub
ArmInsVraddhn
ArmInsVrecpe
ArmInsVrecps
ArmInsVrev16
ArmInsVrev32
ArmInsVrev64
ArmInsVrhadd
ArmInsVrinta
ArmInsVrintm
ArmInsVrintn
ArmInsVrintp
ArmInsVrintr
ArmInsVrintx
ArmInsVrintz
ArmInsVrshl
ArmInsVrshrn
ArmInsVrshr
ArmInsVrsqrte
ArmInsVrsqrts
ArmInsVrsra
ArmInsVrsubhn
ArmInsVseleq
ArmInsVselge
ArmInsVselgt
ArmInsVselvs
ArmInsVshll
ArmInsVshl
ArmInsVshrn
ArmInsVshr
ArmInsVsli
ArmInsVsqrt
ArmInsVsra
ArmInsVsri
ArmInsVst1
ArmInsVst2
ArmInsVst3
ArmInsVst4
ArmInsVstmdb
ArmInsVstmia
ArmInsVstr
ArmInsVsub
ArmInsVsubhn
ArmInsVsubl
ArmInsVsubw
ArmInsVswp
ArmInsVtbl
ArmInsVtbx
ArmInsVcvtr
ArmInsVtrn
ArmInsVtst
ArmInsVuzp
ArmInsVzip
ArmInsAddw
ArmInsAsr
ArmInsDcps1
ArmInsDcps2
ArmInsDcps3
ArmInsIt
ArmInsLsl
ArmInsLsr
ArmInsAsrs
ArmInsLsrs
ArmInsOrn
ArmInsRor
ArmInsRrx
ArmInsSubs
ArmInsSubw
ArmInsTbb
ArmInsTbh
ArmInsCbnz
ArmInsCbz
ArmInsMovs
ArmInsPop
ArmInsPush
ArmInsNop
ArmInsYield
ArmInsWfe
ArmInsWfi
ArmInsSev
ArmInsSevl
ArmInsVpush
ArmInsVpop
ArmInsEnding

Instances

Bounded ArmInsn Source
Enum ArmInsn Source
Eq ArmInsn Source
Show ArmInsn Source

ArmSysregInvalid
ArmSysregSpsrC
ArmSysregSpsrX
ArmSysregSpsrS
ArmSysregSpsrF
ArmSysregCpsrC
ArmSysregCpsrX
ArmSysregCpsrS
ArmSysregCpsrF
ArmSysregApsr
ArmSysregApsrG
ArmSysregApsrNzcvq
ArmSysregApsrNzcvqg
ArmSysregIapsr
ArmSysregIapsrG
ArmSysregIapsrNzcvqg
ArmSysregEapsr
ArmSysregEapsrG
ArmSysregEapsrNzcvqg
ArmSysregXpsr
ArmSysregXpsrG
ArmSysregXpsrNzcvqg
ArmSysregIpsr
ArmSysregEpsr
ArmSysregIepsr
ArmSysregMsp
ArmSysregPsp
ArmSysregPrimask
ArmSysregBasepri
ArmSysregBasepriMax
ArmSysregFaultmask
ArmSysregControl

Bounded ArmSysreg Source
Enum ArmSysreg Source
Eq ArmSysreg Source
Show ArmSysreg Source

ArmVectordataInvalid
ArmVectordataI8
ArmVectordataI16
ArmVectordataI32
ArmVectordataI64
ArmVectordataS8
ArmVectordataS16
ArmVectordataS32
ArmVectordataS64
ArmVectordataU8
ArmVectordataU16
ArmVectordataU32
ArmVectordataU64
ArmVectordataP8
ArmVectordataF32
ArmVectordataF64
ArmVectordataF16f64
ArmVectordataF64f16
ArmVectordataF32f16
ArmVectordataF16f32
ArmVectordataF64f32
ArmVectordataF32f64
ArmVectordataS32f32
ArmVectordataU32f32
ArmVectordataF32s32
ArmVectordataF32u32
ArmVectordataF64s16
ArmVectordataF32s16
ArmVectordataF64s32
ArmVectordataS16f64
ArmVectordataS16f32
ArmVectordataS32f64
ArmVectordataU16f64
ArmVectordataU16f32
ArmVectordataU32f64
ArmVectordataF64u16
ArmVectordataF32u16
ArmVectordataF64u32

ArmGrpInvalid
ArmGrpJump
ArmGrpCrypto
ArmGrpDatabarrier
ArmGrpDivide
ArmGrpFparmv8
ArmGrpMultpro
ArmGrpNeon
ArmGrpT2extractpack
ArmGrpThumb2dsp
ArmGrpTrustzone
ArmGrpV4t
ArmGrpV5t
ArmGrpV5te
ArmGrpV6
ArmGrpV6t2
ArmGrpV7
ArmGrpV8
ArmGrpVfp2
ArmGrpVfp3
ArmGrpVfp4
ArmGrpArm
ArmGrpMclass
ArmGrpNotmclass
ArmGrpThumb
ArmGrpThumb1only
ArmGrpThumb2
ArmGrpPrev8
ArmGrpFpvmlx
ArmGrpMulops
ArmGrpCrc
ArmGrpDpvfp
ArmGrpV6m
ArmGrpEnding

Bounded ArmInsnGroup Source
Enum ArmInsnGroup Source
Eq ArmInsnGroup Source
Show ArmInsnGroup Source