hsverilog-0.1.0: Synthesizable Verilog DSL supporting for multiple clock and reset

Safe Haskell	None
Language	Haskell2010

HsVerilog.Type

Documentation

class Verilog a where Source

Methods

toVerilog :: a -> Text Source

Instances

Verilog Circuit
Verilog Exp
Verilog Assign
Verilog Always
Verilog Stim
Verilog Range

data Range Source

Constructors

Range Integer Integer
RangeBit Integer
Bit

Instances

Eq Range
Read Range
Show Range
Verilog Range

data Signal Source

Constructors

Signal
Fields sname :: Text sbits :: Range sval :: Integer

Instances

Eq Signal
Read Signal
Show Signal

type InstanceName = Text Source

data Instance Source

Constructors

Instance
Fields iname :: InstanceName icircuit :: Circuit

Instances

Eq Instance
Read Instance
Show Instance

data Stim Source

Constructors

Posedge Signal
Negedge Signal

Instances

Eq Stim
Read Stim
Show Stim
Verilog Stim

data Always Source

Constructors

Always
Fields alsig :: Signal alstim :: [Stim] alexp :: Exp

Instances

Eq Always
Read Always
Show Always
Verilog Always

data Assign Source

Constructors

Assign
Fields assig :: Signal asexp :: Exp

Instances

Eq Assign
Read Assign
Show Assign
Verilog Assign

data Exp Source

Constructors

If Exp Exp Exp
Mux Exp Exp Exp
Not Exp
Or Exp Exp
BitOr Exp Exp
And Exp Exp
BitAnd Exp Exp
Add Exp Exp
Sub Exp Exp
Mul Exp Exp
Div Exp Exp
Eq Exp Exp
S Signal
C Integer
NonBlockAssign Exp Exp
BlockAssign Exp Exp

Instances

Eq Exp
Num Exp
Read Exp
Show Exp
Verilog Exp

data Circuit Source

Constructors

Circuit
Fields cname :: Text cinput :: [Signal] coutput :: [Signal] cinout :: [Signal] creg :: [Always] cassign :: [Assign] cinstance :: [Instance] cinstanceConnect :: Map InstanceName [(Signal, Signal)]

Instances

Eq Circuit
Read Circuit
Show Circuit
Verilog Circuit