Safe Haskell | None |
---|---|
Language | Haskell2010 |
HsVerilog.Verilog.DSL
Documentation
initCircuit :: Text -> Circuit Source
hsverilog-0.1.0: Synthesizable Verilog DSL supporting for multiple clock and reset
Safe Haskell | None |
---|---|
Language | Haskell2010 |
HsVerilog.Verilog.DSL
initCircuit :: Text -> Circuit Source