hsverilog-0.1.0: Synthesizable Verilog DSL supporting for multiple clock and reset

Safe Haskell	None
Language	Haskell2010

HsVerilog.Verilog.DSL

Documentation

signal :: Text -> Range -> Signal Source

initCircuit :: Text -> Circuit Source

circuit :: Text -> State Circuit a -> Circuit Source

circuitM :: Monad m => Text -> StateT Circuit m a -> m Circuit Source

input :: Monad m => Text -> Range -> StateT Circuit m Signal Source

output :: Monad m => Text -> Range -> StateT Circuit m Signal Source

inout :: Monad m => Text -> Range -> StateT Circuit m Signal Source

reg :: Monad m => Text -> Range -> [Stim] -> (Exp -> Exp) -> StateT Circuit m Signal Source

reg' :: Monad m => Text -> Range -> [Stim] -> Exp -> StateT Circuit m Signal Source

assign :: Monad m => Signal -> Exp -> StateT Circuit m Signal Source

wire :: Instance -> Text -> Signal Source

inst :: Monad m => Circuit -> Text -> [(Text, Signal)] -> StateT Circuit m Instance Source

connect :: Monad m => Instance -> Text -> Signal -> StateT Circuit m () Source

(.:) :: Instance -> Text -> Signal infix 8 Source

(><) :: Integer -> Integer -> Range infix 8 Source