Copyright | (c) David Cox 2021 |
---|---|
License | BSD 3-Clause |
Maintainer | standardsemiconductor@gmail.com |
Safe Haskell | None |
Language | Haskell2010 |
IO hard IP primitive from Lattice Ice Technology Library
Synopsis
- ioPrim :: BitVector 6 -> Bit -> Bit -> String -> Signal domIn Bit -> Signal domEn Bit -> Clock domIn -> Clock domOut -> Signal domOut Bit -> Signal domOut Bit -> Signal domOut Bit -> (Signal domPin Bit, Signal domIn Bit, Signal domIn Bit)
- data PinInput
- fromPinInput :: PinInput -> BitVector 2
- data PinOutput
- = PinNoOutput
- | PinOutput
- | PinOutputTristate
- | PinOutputEnableRegistered
- | PinOutputRegistered
- | PinOutputRegisteredEnable
- | PinOutputRegisteredEnableRegistered
- | PinOutputDDR
- | PinOutputDDREnable
- | PinOutputDDREnableRegistered
- | PinOutputRegisteredInverted
- | PinOutputRegisteredEnableInverted
- | PinOutputRegisteredEnableRegisteredInverted
- fromPinOutput :: PinOutput -> BitVector 4
- data IOStandard
- fromIOStandard :: IOStandard -> String
- io :: PinInput -> PinOutput -> Bit -> Bit -> IOStandard -> Signal domIn Bit -> Signal domEn Bit -> Clock domIn -> Clock domOut -> Signal domOut Bit -> Signal domOut Bit -> Signal domOut Bit -> (Signal domPin Bit, Signal domIn Bit, Signal domIn Bit)
Documentation
:: BitVector 6 | pinType |
-> Bit | pullup |
-> Bit | negTrigger |
-> String | ioStandard |
-> Signal domIn Bit | latchInputValue |
-> Signal domEn Bit | clockEnable |
-> Clock domIn | inputClk |
-> Clock domOut | outputClk |
-> Signal domOut Bit | outputEnable |
-> Signal domOut Bit | dOut0 |
-> Signal domOut Bit | dOut1 |
-> (Signal domPin Bit, Signal domIn Bit, Signal domIn Bit) | (packagePin, dIn0, dIn1) |
IO primitive, see io for wrapper
Input pin configuration parameter
PinInput | Simple Input pin dIn0 |
PinInputLatch | Disables Internal data changes on the physical input pin by latching the value |
PinInputRegistered | Input data is registered in input cell |
PinInputRegisteredLatch | Disables internal data changes on the physical input pin by latching the value on the input register |
PinInputDDR | Input DDR data is clocked out on rising and falling clock edges. Use the dIn0 and dIn1 pins for DDR operation |
Instances
Eq PinInput Source # | |
Read PinInput Source # | |
Show PinInput Source # | |
Generic PinInput Source # | |
NFDataX PinInput Source # | |
type Rep PinInput Source # | |
Defined in Ice40.IO type Rep PinInput = D1 ('MetaData "PinInput" "Ice40.IO" "ice40-prim-0.2.0.0-8tCVCKJAyDI6582z0dpL1n" 'False) ((C1 ('MetaCons "PinInput" 'PrefixI 'False) (U1 :: Type -> Type) :+: C1 ('MetaCons "PinInputLatch" 'PrefixI 'False) (U1 :: Type -> Type)) :+: (C1 ('MetaCons "PinInputRegistered" 'PrefixI 'False) (U1 :: Type -> Type) :+: (C1 ('MetaCons "PinInputRegisteredLatch" 'PrefixI 'False) (U1 :: Type -> Type) :+: C1 ('MetaCons "PinInputDDR" 'PrefixI 'False) (U1 :: Type -> Type)))) |
fromPinInput :: PinInput -> BitVector 2 Source #
Output pin configuration parameter
PinNoOutput | Disables the output function |
PinOutput | Simple output pin (no enable) |
PinOutputTristate | The output pin may be tristated using the enable |
PinOutputEnableRegistered | The output pin may be tristated using a registered enable signal |
PinOutputRegistered | Output registered (no enable) |
PinOutputRegisteredEnable | Output registered with enable (the enable is not registered) |
PinOutputRegisteredEnableRegistered | Output registered and enable registered |
PinOutputDDR | Output DDR data is clocked out on rising and falling clock edges |
PinOutputDDREnable | Output data is clocked out on rising and falling clock edges |
PinOutputDDREnableRegistered | Output DDR data with registered enable signal |
PinOutputRegisteredInverted | Output registered signal is inverted |
PinOutputRegisteredEnableInverted | Output signal is registered and inverted (no enable function) |
PinOutputRegisteredEnableRegisteredInverted | Output signal is registered and inverted, the enable/tristate control is registered |
Instances
Eq PinOutput Source # | |
Read PinOutput Source # | |
Show PinOutput Source # | |
Generic PinOutput Source # | |
NFDataX PinOutput Source # | |
type Rep PinOutput Source # | |
Defined in Ice40.IO type Rep PinOutput = D1 ('MetaData "PinOutput" "Ice40.IO" "ice40-prim-0.2.0.0-8tCVCKJAyDI6582z0dpL1n" 'False) (((C1 ('MetaCons "PinNoOutput" 'PrefixI 'False) (U1 :: Type -> Type) :+: (C1 ('MetaCons "PinOutput" 'PrefixI 'False) (U1 :: Type -> Type) :+: C1 ('MetaCons "PinOutputTristate" 'PrefixI 'False) (U1 :: Type -> Type))) :+: (C1 ('MetaCons "PinOutputEnableRegistered" 'PrefixI 'False) (U1 :: Type -> Type) :+: (C1 ('MetaCons "PinOutputRegistered" 'PrefixI 'False) (U1 :: Type -> Type) :+: C1 ('MetaCons "PinOutputRegisteredEnable" 'PrefixI 'False) (U1 :: Type -> Type)))) :+: ((C1 ('MetaCons "PinOutputRegisteredEnableRegistered" 'PrefixI 'False) (U1 :: Type -> Type) :+: (C1 ('MetaCons "PinOutputDDR" 'PrefixI 'False) (U1 :: Type -> Type) :+: C1 ('MetaCons "PinOutputDDREnable" 'PrefixI 'False) (U1 :: Type -> Type))) :+: ((C1 ('MetaCons "PinOutputDDREnableRegistered" 'PrefixI 'False) (U1 :: Type -> Type) :+: C1 ('MetaCons "PinOutputRegisteredInverted" 'PrefixI 'False) (U1 :: Type -> Type)) :+: (C1 ('MetaCons "PinOutputRegisteredEnableInverted" 'PrefixI 'False) (U1 :: Type -> Type) :+: C1 ('MetaCons "PinOutputRegisteredEnableRegisteredInverted" 'PrefixI 'False) (U1 :: Type -> Type))))) |
fromPinOutput :: PinOutput -> BitVector 4 Source #
data IOStandard Source #
Input-Output Standards
Instances
Eq IOStandard Source # | |
Defined in Ice40.IO (==) :: IOStandard -> IOStandard -> Bool # (/=) :: IOStandard -> IOStandard -> Bool # | |
Read IOStandard Source # | |
Defined in Ice40.IO readsPrec :: Int -> ReadS IOStandard # readList :: ReadS [IOStandard] # readPrec :: ReadPrec IOStandard # readListPrec :: ReadPrec [IOStandard] # | |
Show IOStandard Source # | |
Defined in Ice40.IO showsPrec :: Int -> IOStandard -> ShowS # show :: IOStandard -> String # showList :: [IOStandard] -> ShowS # | |
Generic IOStandard Source # | |
Defined in Ice40.IO type Rep IOStandard :: Type -> Type # from :: IOStandard -> Rep IOStandard x # to :: Rep IOStandard x -> IOStandard # | |
type Rep IOStandard Source # | |
fromIOStandard :: IOStandard -> String Source #
:: PinInput | |
-> PinOutput | |
-> Bit | pullUp |
-> Bit | negTrigger |
-> IOStandard | |
-> Signal domIn Bit | latchInputValue |
-> Signal domEn Bit | clockEnable |
-> Clock domIn | inputClk |
-> Clock domOut | outputClk |
-> Signal domOut Bit | outputEnable |
-> Signal domOut Bit | dOut0 |
-> Signal domOut Bit | dOut1 |
-> (Signal domPin Bit, Signal domIn Bit, Signal domIn Bit) | (packagePin, dIn0, dIn1) |
IO primitive