module Ice40.Osc
( lf10kHz
, hf48Mhz
, hf24Mhz
, hf12Mhz
, hf6Mhz
) where
import Clash.Prelude
import Clash.Signal.Internal
import Clash.Annotations.Primitive
import Data.String.Interpolate (i)
import Data.String.Interpolate.Util (unindent)
import Ice40.Clock
{-# ANN lf10kHz (InlinePrimitive [Verilog] $ unindent [i|
[ { "BlackBox" :
{ "name" : "Ice40.Osc.lf10kHz"
, "kind" : "Declaration"
, "type" :
"lf10kHz
:: Signal dom Bool -- ARG[0] clkLfPu
-> Signal dom Bool -- ARG[1] clkLfEn
-> Clock Lattice10kHz"
, "template" :
"//SB_LFOSC begin
SB_LFOSC ~GENSYM[sb_lfosc_inst][0] (
.CLKLFEN (~ARG[0]),
.CLKLFPU (~ARG[1]),
.CLKLF (~RESULT)
);
//SB_LFOSC end"
}
}
]
|]) #-}
{-# NOINLINE lf10kHz #-}
lf10kHz
:: Signal dom Bool
-> Signal dom Bool
-> Clock Lattice10kHz
lf10kHz :: Signal dom Bool -> Signal dom Bool -> Clock Lattice10kHz
lf10kHz !Signal dom Bool
_ !Signal dom Bool
_ = SSymbol Lattice10kHz -> Clock Lattice10kHz
forall (dom :: Domain). SSymbol dom -> Clock dom
Clock SSymbol Lattice10kHz
forall (s :: Domain). KnownSymbol s => SSymbol s
SSymbol
{-# ANN hfPrim (InlinePrimitive [Verilog] $ unindent [i|
[ { "BlackBox" :
{ "name" : "Ice40.Osc.hfPrim"
, "kind" : "Declaration"
, "type" :
"hfPrim
:: KnownDomain dom -- ARG[0]
=> KnownDomain dom' -- ARG[1]
=> String -- ARG[2] clkhfdiv
-> Signal dom Bool -- ARG[3] clkhfen
-> Signal dom Bool -- ARG[4] clkhfpu
-> Clock dom' -- clkhf"
, "template" :
"//SB_HFOSC begin
SB_HFOSC #( .CLKHF_DIV(~ARG[2]) ) ~GENSYM[sb_hfosc_inst][0] (
.CLKHFEN (~ARG[3]),
.CLKHFPU (~ARG[4]),
.CLKHF (~RESULT)
);
//SB_HFOSC end"
}
}
]
|]) #-}
{-# NOINLINE hfPrim #-}
hfPrim
:: KnownDomain dom
=> KnownDomain dom'
=> String
-> Signal dom Bool
-> Signal dom Bool
-> Clock dom'
hfPrim :: String -> Signal dom Bool -> Signal dom Bool -> Clock dom'
hfPrim !String
_ !Signal dom Bool
_ !Signal dom Bool
_ = SSymbol dom' -> Clock dom'
forall (dom :: Domain). SSymbol dom -> Clock dom
Clock SSymbol dom'
forall (s :: Domain). KnownSymbol s => SSymbol s
SSymbol
hf48Mhz
:: KnownDomain dom
=> Signal dom Bool
-> Signal dom Bool
-> Clock Lattice48Mhz
hf48Mhz :: Signal dom Bool -> Signal dom Bool -> Clock Lattice48Mhz
hf48Mhz = String -> Signal dom Bool -> Signal dom Bool -> Clock Lattice48Mhz
forall (dom :: Domain) (dom' :: Domain).
(KnownDomain dom, KnownDomain dom') =>
String -> Signal dom Bool -> Signal dom Bool -> Clock dom'
hfPrim String
"0b00"
hf24Mhz
:: KnownDomain dom
=> Signal dom Bool
-> Signal dom Bool
-> Clock Lattice24Mhz
hf24Mhz :: Signal dom Bool -> Signal dom Bool -> Clock Lattice24Mhz
hf24Mhz = String -> Signal dom Bool -> Signal dom Bool -> Clock Lattice24Mhz
forall (dom :: Domain) (dom' :: Domain).
(KnownDomain dom, KnownDomain dom') =>
String -> Signal dom Bool -> Signal dom Bool -> Clock dom'
hfPrim String
"0b01"
hf12Mhz
:: KnownDomain dom
=> Signal dom Bool
-> Signal dom Bool
-> Clock Lattice12Mhz
hf12Mhz :: Signal dom Bool -> Signal dom Bool -> Clock Lattice12Mhz
hf12Mhz = String -> Signal dom Bool -> Signal dom Bool -> Clock Lattice12Mhz
forall (dom :: Domain) (dom' :: Domain).
(KnownDomain dom, KnownDomain dom') =>
String -> Signal dom Bool -> Signal dom Bool -> Clock dom'
hfPrim String
"0b10"
hf6Mhz
:: KnownDomain dom
=> Signal dom Bool
-> Signal dom Bool
-> Clock Lattice6Mhz
hf6Mhz :: Signal dom Bool -> Signal dom Bool -> Clock Lattice6Mhz
hf6Mhz = String -> Signal dom Bool -> Signal dom Bool -> Clock Lattice6Mhz
forall (dom :: Domain) (dom' :: Domain).
(KnownDomain dom, KnownDomain dom') =>
String -> Signal dom Bool -> Signal dom Bool -> Clock dom'
hfPrim String
"0b11"