module Ice40.IO where
import Clash.Prelude
import Clash.Annotations.Primitive
import Data.String.Interpolate (i)
import Data.String.Interpolate.Util (unindent)
{-# ANN ioPrim (InlinePrimitive [Verilog] $ unindent [i|
[ { "BlackBox" :
{ "name" : "Ice40.IO.ioPrim"
, "kind" : "Declaration"
, "type" :
"ioPrim
:: BitVector 6 -- ARG[0] pinType
-> Bit -- ARG[1] pullup
-> Bit -- ARG[2] negTrigger
-> String -- ARG[3] ioStandard
-> Signal domIn Bit -- ARG[4] latchInputValue
-> Signal domEn Bit -- ARG[5] clockEnable
-> Clock domIn -- ARG[6] inputClk
-> Clock domOut -- ARG[7] outputClk
-> Signal domOut Bit -- ARG[8] outputEnable
-> Signal domOut Bit -- ARG[9] dOut0
-> Signal domOut Bit -- ARG[10] dOut1
-> ( Signal domPin Bit -- packagePin
, Signal domIn Bit -- dIn0
, Signal domIn Bit -- dIn1
)"
, "template" :
"//SB_IO begin
wire ~GENSYM[package_pin][0];
wire ~GENSYM[d_in_0][1];
wire ~GENSYM[d_in_1][2];
SB_IO #(
.PIN_TYPE ( ~ARG[0] ),
.PULLUP ( ~ARG[1] ),
.NEG_TRIGGER ( ~ARG[2] ),
.IO_STANDARD ( ~ARG[3] )
) ~GENSYM[sb_io_inst][3] (
.PACKAGE_PIN ( ~SYM[0] ),
.LATCH_INPUT_VALUE( ~ARG[4] ),
.CLOCK_ENABLE ( ~ARG[5] ),
.INPUT_CLK ( ~ARG[6] ),
.OUTPUT_CLK ( ~ARG[7] ),
.OUTPUT_ENABLE ( ~ARG[8] ),
.D_OUT_0 ( ~ARG[9] ),
.D_OUT_1 ( ~ARG[10] ),
.D_IN_0 ( ~SYM[1] ),
.D_IN_1 ( ~SYM[2] )
);
assign ~RESULT = { ~SYM[0], ~SYM[1], ~SYM[2] };
//SB_IO end"
}
}
]
|]) #-}
{-# NOINLINE ioPrim #-}
ioPrim
:: BitVector 6
-> Bit
-> Bit
-> String
-> Signal domIn Bit
-> Signal domEn Bit
-> Clock domIn
-> Clock domOut
-> Signal domOut Bit
-> Signal domOut Bit
-> Signal domOut Bit
-> ( Signal domPin Bit
, Signal domIn Bit
, Signal domIn Bit
)
ioPrim :: BitVector 6
-> Bit
-> Bit
-> String
-> Signal domIn Bit
-> Signal domEn Bit
-> Clock domIn
-> Clock domOut
-> Signal domOut Bit
-> Signal domOut Bit
-> Signal domOut Bit
-> (Signal domPin Bit, Signal domIn Bit, Signal domIn Bit)
ioPrim !BitVector 6
_ !Bit
_ !Bit
_ !String
_ !Signal domIn Bit
_ !Signal domEn Bit
_ !Clock domIn
_ !Clock domOut
_ !Signal domOut Bit
_ !Signal domOut Bit
_ !Signal domOut Bit
_ = (Bit -> Signal domPin Bit
forall (f :: Type -> Type) a. Applicative f => a -> f a
pure Bit
0, Bit -> Signal domIn Bit
forall (f :: Type -> Type) a. Applicative f => a -> f a
pure Bit
0, Bit -> Signal domIn Bit
forall (f :: Type -> Type) a. Applicative f => a -> f a
pure Bit
0)
data PinInput = PinInput
| PinInputLatch
| PinInputRegistered
| PinInputRegisteredLatch
| PinInputDDR
deriving stock ((forall x. PinInput -> Rep PinInput x)
-> (forall x. Rep PinInput x -> PinInput) -> Generic PinInput
forall x. Rep PinInput x -> PinInput
forall x. PinInput -> Rep PinInput x
forall a.
(forall x. a -> Rep a x) -> (forall x. Rep a x -> a) -> Generic a
$cto :: forall x. Rep PinInput x -> PinInput
$cfrom :: forall x. PinInput -> Rep PinInput x
Generic, Int -> PinInput -> ShowS
[PinInput] -> ShowS
PinInput -> String
(Int -> PinInput -> ShowS)
-> (PinInput -> String) -> ([PinInput] -> ShowS) -> Show PinInput
forall a.
(Int -> a -> ShowS) -> (a -> String) -> ([a] -> ShowS) -> Show a
showList :: [PinInput] -> ShowS
$cshowList :: [PinInput] -> ShowS
show :: PinInput -> String
$cshow :: PinInput -> String
showsPrec :: Int -> PinInput -> ShowS
$cshowsPrec :: Int -> PinInput -> ShowS
Show, ReadPrec [PinInput]
ReadPrec PinInput
Int -> ReadS PinInput
ReadS [PinInput]
(Int -> ReadS PinInput)
-> ReadS [PinInput]
-> ReadPrec PinInput
-> ReadPrec [PinInput]
-> Read PinInput
forall a.
(Int -> ReadS a)
-> ReadS [a] -> ReadPrec a -> ReadPrec [a] -> Read a
readListPrec :: ReadPrec [PinInput]
$creadListPrec :: ReadPrec [PinInput]
readPrec :: ReadPrec PinInput
$creadPrec :: ReadPrec PinInput
readList :: ReadS [PinInput]
$creadList :: ReadS [PinInput]
readsPrec :: Int -> ReadS PinInput
$creadsPrec :: Int -> ReadS PinInput
Read, PinInput -> PinInput -> Bool
(PinInput -> PinInput -> Bool)
-> (PinInput -> PinInput -> Bool) -> Eq PinInput
forall a. (a -> a -> Bool) -> (a -> a -> Bool) -> Eq a
/= :: PinInput -> PinInput -> Bool
$c/= :: PinInput -> PinInput -> Bool
== :: PinInput -> PinInput -> Bool
$c== :: PinInput -> PinInput -> Bool
Eq)
deriving anyclass HasCallStack => String -> PinInput
PinInput -> Bool
PinInput -> ()
PinInput -> PinInput
(HasCallStack => String -> PinInput)
-> (PinInput -> Bool)
-> (PinInput -> PinInput)
-> (PinInput -> ())
-> NFDataX PinInput
forall a.
(HasCallStack => String -> a)
-> (a -> Bool) -> (a -> a) -> (a -> ()) -> NFDataX a
rnfX :: PinInput -> ()
$crnfX :: PinInput -> ()
ensureSpine :: PinInput -> PinInput
$censureSpine :: PinInput -> PinInput
hasUndefined :: PinInput -> Bool
$chasUndefined :: PinInput -> Bool
deepErrorX :: String -> PinInput
$cdeepErrorX :: HasCallStack => String -> PinInput
NFDataX
fromPinInput :: PinInput -> BitVector 2
fromPinInput :: PinInput -> BitVector 2
fromPinInput = \case
PinInput
PinInput -> BitVector 2
0b01
PinInput
PinInputLatch -> BitVector 2
0b11
PinInput
PinInputRegistered -> BitVector 2
0b00
PinInput
PinInputRegisteredLatch -> BitVector 2
0b10
PinInput
PinInputDDR -> BitVector 2
0b00
data PinOutput = PinNoOutput
| PinOutput
| PinOutputTristate
| PinOutputEnableRegistered
| PinOutputRegistered
| PinOutputRegisteredEnable
| PinOutputRegisteredEnableRegistered
| PinOutputDDR
| PinOutputDDREnable
| PinOutputDDREnableRegistered
| PinOutputRegisteredInverted
| PinOutputRegisteredEnableInverted
| PinOutputRegisteredEnableRegisteredInverted
deriving stock ((forall x. PinOutput -> Rep PinOutput x)
-> (forall x. Rep PinOutput x -> PinOutput) -> Generic PinOutput
forall x. Rep PinOutput x -> PinOutput
forall x. PinOutput -> Rep PinOutput x
forall a.
(forall x. a -> Rep a x) -> (forall x. Rep a x -> a) -> Generic a
$cto :: forall x. Rep PinOutput x -> PinOutput
$cfrom :: forall x. PinOutput -> Rep PinOutput x
Generic, Int -> PinOutput -> ShowS
[PinOutput] -> ShowS
PinOutput -> String
(Int -> PinOutput -> ShowS)
-> (PinOutput -> String)
-> ([PinOutput] -> ShowS)
-> Show PinOutput
forall a.
(Int -> a -> ShowS) -> (a -> String) -> ([a] -> ShowS) -> Show a
showList :: [PinOutput] -> ShowS
$cshowList :: [PinOutput] -> ShowS
show :: PinOutput -> String
$cshow :: PinOutput -> String
showsPrec :: Int -> PinOutput -> ShowS
$cshowsPrec :: Int -> PinOutput -> ShowS
Show, ReadPrec [PinOutput]
ReadPrec PinOutput
Int -> ReadS PinOutput
ReadS [PinOutput]
(Int -> ReadS PinOutput)
-> ReadS [PinOutput]
-> ReadPrec PinOutput
-> ReadPrec [PinOutput]
-> Read PinOutput
forall a.
(Int -> ReadS a)
-> ReadS [a] -> ReadPrec a -> ReadPrec [a] -> Read a
readListPrec :: ReadPrec [PinOutput]
$creadListPrec :: ReadPrec [PinOutput]
readPrec :: ReadPrec PinOutput
$creadPrec :: ReadPrec PinOutput
readList :: ReadS [PinOutput]
$creadList :: ReadS [PinOutput]
readsPrec :: Int -> ReadS PinOutput
$creadsPrec :: Int -> ReadS PinOutput
Read, PinOutput -> PinOutput -> Bool
(PinOutput -> PinOutput -> Bool)
-> (PinOutput -> PinOutput -> Bool) -> Eq PinOutput
forall a. (a -> a -> Bool) -> (a -> a -> Bool) -> Eq a
/= :: PinOutput -> PinOutput -> Bool
$c/= :: PinOutput -> PinOutput -> Bool
== :: PinOutput -> PinOutput -> Bool
$c== :: PinOutput -> PinOutput -> Bool
Eq)
deriving anyclass HasCallStack => String -> PinOutput
PinOutput -> Bool
PinOutput -> ()
PinOutput -> PinOutput
(HasCallStack => String -> PinOutput)
-> (PinOutput -> Bool)
-> (PinOutput -> PinOutput)
-> (PinOutput -> ())
-> NFDataX PinOutput
forall a.
(HasCallStack => String -> a)
-> (a -> Bool) -> (a -> a) -> (a -> ()) -> NFDataX a
rnfX :: PinOutput -> ()
$crnfX :: PinOutput -> ()
ensureSpine :: PinOutput -> PinOutput
$censureSpine :: PinOutput -> PinOutput
hasUndefined :: PinOutput -> Bool
$chasUndefined :: PinOutput -> Bool
deepErrorX :: String -> PinOutput
$cdeepErrorX :: HasCallStack => String -> PinOutput
NFDataX
fromPinOutput :: PinOutput -> BitVector 4
fromPinOutput :: PinOutput -> BitVector 4
fromPinOutput = \case
PinOutput
PinNoOutput -> BitVector 4
0b0000
PinOutput
PinOutput -> BitVector 4
0b0110
PinOutput
PinOutputTristate -> BitVector 4
0b1010
PinOutput
PinOutputEnableRegistered -> BitVector 4
0b1110
PinOutput
PinOutputRegistered -> BitVector 4
0b0101
PinOutput
PinOutputRegisteredEnable -> BitVector 4
0b1001
PinOutput
PinOutputRegisteredEnableRegistered -> BitVector 4
0b1101
PinOutput
PinOutputDDR -> BitVector 4
0b0100
PinOutput
PinOutputDDREnable -> BitVector 4
0b1000
PinOutput
PinOutputDDREnableRegistered -> BitVector 4
0b1100
PinOutput
PinOutputRegisteredInverted -> BitVector 4
0b0111
PinOutput
PinOutputRegisteredEnableInverted -> BitVector 4
0b1011
PinOutput
PinOutputRegisteredEnableRegisteredInverted -> BitVector 4
0b1111
data IOStandard = SBLVCMOS
| SBLVDSINPUT
deriving ((forall x. IOStandard -> Rep IOStandard x)
-> (forall x. Rep IOStandard x -> IOStandard) -> Generic IOStandard
forall x. Rep IOStandard x -> IOStandard
forall x. IOStandard -> Rep IOStandard x
forall a.
(forall x. a -> Rep a x) -> (forall x. Rep a x -> a) -> Generic a
$cto :: forall x. Rep IOStandard x -> IOStandard
$cfrom :: forall x. IOStandard -> Rep IOStandard x
Generic, Int -> IOStandard -> ShowS
[IOStandard] -> ShowS
IOStandard -> String
(Int -> IOStandard -> ShowS)
-> (IOStandard -> String)
-> ([IOStandard] -> ShowS)
-> Show IOStandard
forall a.
(Int -> a -> ShowS) -> (a -> String) -> ([a] -> ShowS) -> Show a
showList :: [IOStandard] -> ShowS
$cshowList :: [IOStandard] -> ShowS
show :: IOStandard -> String
$cshow :: IOStandard -> String
showsPrec :: Int -> IOStandard -> ShowS
$cshowsPrec :: Int -> IOStandard -> ShowS
Show, ReadPrec [IOStandard]
ReadPrec IOStandard
Int -> ReadS IOStandard
ReadS [IOStandard]
(Int -> ReadS IOStandard)
-> ReadS [IOStandard]
-> ReadPrec IOStandard
-> ReadPrec [IOStandard]
-> Read IOStandard
forall a.
(Int -> ReadS a)
-> ReadS [a] -> ReadPrec a -> ReadPrec [a] -> Read a
readListPrec :: ReadPrec [IOStandard]
$creadListPrec :: ReadPrec [IOStandard]
readPrec :: ReadPrec IOStandard
$creadPrec :: ReadPrec IOStandard
readList :: ReadS [IOStandard]
$creadList :: ReadS [IOStandard]
readsPrec :: Int -> ReadS IOStandard
$creadsPrec :: Int -> ReadS IOStandard
Read, IOStandard -> IOStandard -> Bool
(IOStandard -> IOStandard -> Bool)
-> (IOStandard -> IOStandard -> Bool) -> Eq IOStandard
forall a. (a -> a -> Bool) -> (a -> a -> Bool) -> Eq a
/= :: IOStandard -> IOStandard -> Bool
$c/= :: IOStandard -> IOStandard -> Bool
== :: IOStandard -> IOStandard -> Bool
$c== :: IOStandard -> IOStandard -> Bool
Eq)
fromIOStandard :: IOStandard -> String
fromIOStandard :: IOStandard -> String
fromIOStandard = \case
IOStandard
SBLVCMOS -> String
"SB_LVCMOS"
IOStandard
SBLVDSINPUT -> String
"SB_LVDS_INPUT"
io
:: PinInput
-> PinOutput
-> Bit
-> Bit
-> IOStandard
-> Signal domIn Bit
-> Signal domEn Bit
-> Clock domIn
-> Clock domOut
-> Signal domOut Bit
-> Signal domOut Bit
-> Signal domOut Bit
-> ( Signal domPin Bit
, Signal domIn Bit
, Signal domIn Bit
)
io :: PinInput
-> PinOutput
-> Bit
-> Bit
-> IOStandard
-> Signal domIn Bit
-> Signal domEn Bit
-> Clock domIn
-> Clock domOut
-> Signal domOut Bit
-> Signal domOut Bit
-> Signal domOut Bit
-> (Signal domPin Bit, Signal domIn Bit, Signal domIn Bit)
io PinInput
pinInput PinOutput
pinOutput Bit
pullUp Bit
negTrigger IOStandard
ioStandard
= BitVector 6
-> Bit
-> Bit
-> String
-> Signal domIn Bit
-> Signal domEn Bit
-> Clock domIn
-> Clock domOut
-> Signal domOut Bit
-> Signal domOut Bit
-> Signal domOut Bit
-> (Signal domPin Bit, Signal domIn Bit, Signal domIn Bit)
forall (domIn :: Domain) (domEn :: Domain) (domOut :: Domain)
(domPin :: Domain).
BitVector 6
-> Bit
-> Bit
-> String
-> Signal domIn Bit
-> Signal domEn Bit
-> Clock domIn
-> Clock domOut
-> Signal domOut Bit
-> Signal domOut Bit
-> Signal domOut Bit
-> (Signal domPin Bit, Signal domIn Bit, Signal domIn Bit)
ioPrim
(PinOutput -> BitVector 4
fromPinOutput PinOutput
pinOutput BitVector 4 -> BitVector 2 -> BitVector (4 + 2)
forall (m :: Nat) (n :: Nat).
KnownNat m =>
BitVector n -> BitVector m -> BitVector (n + m)
++# PinInput -> BitVector 2
fromPinInput PinInput
pinInput)
Bit
pullUp
Bit
negTrigger
(IOStandard -> String
fromIOStandard IOStandard
ioStandard)