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Build #1 for language-vhdl-0.1.2.3

[all reports]

Package	language-vhdl-0.1.2.3

Install	InstallOk
Docs	Ok
Tests	NotTried

Time submitted	2015-12-11 09:17:01.091071 UTC
Compiler	ghc-7.10.2
OS	linux
Arch	x86_64
Dependencies	pretty-1.1.2.0, base-4.8.1.0
Flags	none

Code Coverage

No Code Coverage was submitted for this report.

Build log

[view raw]

Resolving dependencies...
Downloading language-vhdl-0.1.2.3...
Configuring language-vhdl-0.1.2.3...
Building language-vhdl-0.1.2.3...
Preprocessing library language-vhdl-0.1.2.3...
[1 of 3] Compiling Language.VHDL.Syntax ( src/Language/VHDL/Syntax.hs, dist/build/Language/VHDL/Syntax.o )
[2 of 3] Compiling Language.VHDL.Pretty ( src/Language/VHDL/Pretty.hs, dist/build/Language/VHDL/Pretty.o )
[3 of 3] Compiling Language.VHDL    ( src/Language/VHDL.hs, dist/build/Language/VHDL.o )
In-place registering language-vhdl-0.1.2.3...
Running Haddock for language-vhdl-0.1.2.3...
Running hscolour for language-vhdl-0.1.2.3...
Preprocessing library language-vhdl-0.1.2.3...
Preprocessing library language-vhdl-0.1.2.3...
Haddock coverage:
  36% (133 /368) in 'Language.VHDL.Syntax'
  Missing documentation for:
    Module header
    EntityDeclaration (src/Language/VHDL/Syntax.hs:24)
    EntityHeader (src/Language/VHDL/Syntax.hs:43)
    GenericClause (src/Language/VHDL/Syntax.hs:49)
    PortClause (src/Language/VHDL/Syntax.hs:52)
    GenericList (src/Language/VHDL/Syntax.hs:61)
    PortList (src/Language/VHDL/Syntax.hs:69)
    EntityDeclarativePart (src/Language/VHDL/Syntax.hs:95)
    EntityDeclarativeItem (src/Language/VHDL/Syntax.hs:97)
    EntityStatementPart (src/Language/VHDL/Syntax.hs:127)
    EntityStatement (src/Language/VHDL/Syntax.hs:129)
    ArchitectureBody (src/Language/VHDL/Syntax.hs:147)
    ArchitectureDeclarativePart (src/Language/VHDL/Syntax.hs:181)
    BlockDeclarativeItem (src/Language/VHDL/Syntax.hs:183)
    ArchitectureStatementPart (src/Language/VHDL/Syntax.hs:210)
    ConfigurationDeclaration (src/Language/VHDL/Syntax.hs:231)
    ConfigurationDeclarativePart (src/Language/VHDL/Syntax.hs:239)
    ConfigurationDeclarativeItem (src/Language/VHDL/Syntax.hs:241)
    BlockConfiguration (src/Language/VHDL/Syntax.hs:270)
    BlockSpecification (src/Language/VHDL/Syntax.hs:277)
    IndexSpecification (src/Language/VHDL/Syntax.hs:283)
    ConfigurationItem (src/Language/VHDL/Syntax.hs:288)
    ComponentConfiguration (src/Language/VHDL/Syntax.hs:304)
    SubprogramDeclaration (src/Language/VHDL/Syntax.hs:336)
    SubprogramSpecification (src/Language/VHDL/Syntax.hs:338)
    Designator (src/Language/VHDL/Syntax.hs:351)
    OperatorSymbol (src/Language/VHDL/Syntax.hs:356)
    FormalParameterList (src/Language/VHDL/Syntax.hs:364)
    SubprogramBody (src/Language/VHDL/Syntax.hs:417)
    SubprogramDeclarativePart (src/Language/VHDL/Syntax.hs:426)
    SubprogramDeclarativeItem (src/Language/VHDL/Syntax.hs:428)
    SubprogramStatementPart (src/Language/VHDL/Syntax.hs:444)
    SubprogramKind (src/Language/VHDL/Syntax.hs:446)
    Signature (src/Language/VHDL/Syntax.hs:465)
    PackageDeclaration (src/Language/VHDL/Syntax.hs:502)
    PackageDeclarativePart (src/Language/VHDL/Syntax.hs:508)
    PackageDeclarativeItem (src/Language/VHDL/Syntax.hs:510)
    PackageBody (src/Language/VHDL/Syntax.hs:554)
    PackageBodyDeclarativePart (src/Language/VHDL/Syntax.hs:560)
    PackageBodyDeclarativeItem (src/Language/VHDL/Syntax.hs:562)
    ScalarTypeDefinition (src/Language/VHDL/Syntax.hs:608)
    RangeConstraint (src/Language/VHDL/Syntax.hs:615)
    Range (src/Language/VHDL/Syntax.hs:618)
    Direction (src/Language/VHDL/Syntax.hs:627)
    EnumerationTypeDefinition (src/Language/VHDL/Syntax.hs:639)
    EnumerationLiteral (src/Language/VHDL/Syntax.hs:642)
    IntegerTypeDefinition (src/Language/VHDL/Syntax.hs:658)
    PhysicalTypeDefinition (src/Language/VHDL/Syntax.hs:682)
    PrimaryUnitDeclaration (src/Language/VHDL/Syntax.hs:690)
    SecondaryUnitDeclaration (src/Language/VHDL/Syntax.hs:692)
    PhysicalLiteral (src/Language/VHDL/Syntax.hs:695)
    FloatingTypeDefinition (src/Language/VHDL/Syntax.hs:712)
    CompositeTypeDefinition (src/Language/VHDL/Syntax.hs:727)
    ArrayTypeDefinition (src/Language/VHDL/Syntax.hs:753)
    UnconstrainedArrayDefinition (src/Language/VHDL/Syntax.hs:758)
    ConstrainedArrayDefinition (src/Language/VHDL/Syntax.hs:764)
    IndexSubtypeDefinition (src/Language/VHDL/Syntax.hs:770)
    IndexConstraint (src/Language/VHDL/Syntax.hs:773)
    DiscreteRange (src/Language/VHDL/Syntax.hs:776)
    RecordTypeDefinition (src/Language/VHDL/Syntax.hs:808)
    ElementDeclaration (src/Language/VHDL/Syntax.hs:814)
    IdentifierList (src/Language/VHDL/Syntax.hs:820)
    ElementSubtypeDefinition (src/Language/VHDL/Syntax.hs:822)
    AccessTypeDefinition (src/Language/VHDL/Syntax.hs:830)
    IncompleteTypeDeclaration (src/Language/VHDL/Syntax.hs:839)
    FileTypeDefinition (src/Language/VHDL/Syntax.hs:853)
    Declaration (src/Language/VHDL/Syntax.hs:890)
    TypeDeclaration (src/Language/VHDL/Syntax.hs:923)
    FullTypeDeclaration (src/Language/VHDL/Syntax.hs:926)
    TypeDefinition (src/Language/VHDL/Syntax.hs:932)
    SubtypeDeclaration (src/Language/VHDL/Syntax.hs:958)
    SubtypeIndication (src/Language/VHDL/Syntax.hs:964)
    TypeMark (src/Language/VHDL/Syntax.hs:971)
    Constraint (src/Language/VHDL/Syntax.hs:974)
    ObjectDeclaration (src/Language/VHDL/Syntax.hs:990)
    ConstantDeclaration (src/Language/VHDL/Syntax.hs:1004)
    SignalDeclaration (src/Language/VHDL/Syntax.hs:1020)
    SignalKind (src/Language/VHDL/Syntax.hs:1028)
    VariableDeclaration (src/Language/VHDL/Syntax.hs:1038)
    FileDeclaration (src/Language/VHDL/Syntax.hs:1058)
    FileOpenInformation (src/Language/VHDL/Syntax.hs:1065)
    FileLogicalName (src/Language/VHDL/Syntax.hs:1071)
    InterfaceDeclaration (src/Language/VHDL/Syntax.hs:1097)
    Mode (src/Language/VHDL/Syntax.hs:1122)
    InterfaceList (src/Language/VHDL/Syntax.hs:1133)
    InterfaceElement (src/Language/VHDL/Syntax.hs:1136)
    AssociationElement (src/Language/VHDL/Syntax.hs:1170)
    AssociationList (src/Language/VHDL/Syntax.hs:1176)
    FormalDesignator (src/Language/VHDL/Syntax.hs:1179)
    FormalPart (src/Language/VHDL/Syntax.hs:1185)
    ActualDesignator (src/Language/VHDL/Syntax.hs:1191)
    ActualPart (src/Language/VHDL/Syntax.hs:1199)
    AliasDeclaration (src/Language/VHDL/Syntax.hs:1214)
    AliasDesignator (src/Language/VHDL/Syntax.hs:1222)
    AttributeDeclaration (src/Language/VHDL/Syntax.hs:1241)
    ComponentDeclaration (src/Language/VHDL/Syntax.hs:1257)
    GroupTemplateDeclaration (src/Language/VHDL/Syntax.hs:1277)
    EntityClassEntryList (src/Language/VHDL/Syntax.hs:1283)
    EntityClassEntry (src/Language/VHDL/Syntax.hs:1285)
    GroupDeclaration (src/Language/VHDL/Syntax.hs:1302)
    GroupConstituentList (src/Language/VHDL/Syntax.hs:1309)
    GroupConstituent (src/Language/VHDL/Syntax.hs:1311)
    AttributeSpecification (src/Language/VHDL/Syntax.hs:1351)
    EntitySpecification (src/Language/VHDL/Syntax.hs:1358)
    EntityClass (src/Language/VHDL/Syntax.hs:1364)
    EntityNameList (src/Language/VHDL/Syntax.hs:1373)
    EntityDesignator (src/Language/VHDL/Syntax.hs:1379)
    EntityTag (src/Language/VHDL/Syntax.hs:1385)
    ConfigurationSpecification (src/Language/VHDL/Syntax.hs:1407)
    ComponentSpecification (src/Language/VHDL/Syntax.hs:1413)
    InstantiationList (src/Language/VHDL/Syntax.hs:1419)
    BindingIndication (src/Language/VHDL/Syntax.hs:1434)
    EntityAspect (src/Language/VHDL/Syntax.hs:1450)
    GenericMapAspect (src/Language/VHDL/Syntax.hs:1466)
    PortMapAspect (src/Language/VHDL/Syntax.hs:1469)
    DisconnectionSpecification (src/Language/VHDL/Syntax.hs:1492)
    GuardedSignalSpecification (src/Language/VHDL/Syntax.hs:1498)
    SignalList (src/Language/VHDL/Syntax.hs:1504)
    Name (src/Language/VHDL/Syntax.hs:1534)
    Prefix (src/Language/VHDL/Syntax.hs:1543)
    SimpleName (src/Language/VHDL/Syntax.hs:1554)
    SelectedName (src/Language/VHDL/Syntax.hs:1568)
    Suffix (src/Language/VHDL/Syntax.hs:1574)
    IndexedName (src/Language/VHDL/Syntax.hs:1587)
    SliceName (src/Language/VHDL/Syntax.hs:1599)
    AttributeName (src/Language/VHDL/Syntax.hs:1614)
    AttributeDesignator (src/Language/VHDL/Syntax.hs:1622)
    Expression (src/Language/VHDL/Syntax.hs:1671)
    Relation (src/Language/VHDL/Syntax.hs:1680)
    ShiftExpression (src/Language/VHDL/Syntax.hs:1686)
    SimpleExpression (src/Language/VHDL/Syntax.hs:1692)
    Term (src/Language/VHDL/Syntax.hs:1699)
    Factor (src/Language/VHDL/Syntax.hs:1705)
    Primary (src/Language/VHDL/Syntax.hs:1711)
    LogicalOperator (src/Language/VHDL/Syntax.hs:1740)
    RelationalOperator (src/Language/VHDL/Syntax.hs:1743)
    ShiftOperator (src/Language/VHDL/Syntax.hs:1746)
    AddingOperator (src/Language/VHDL/Syntax.hs:1749)
    Sign (src/Language/VHDL/Syntax.hs:1752)
    MultiplyingOperator (src/Language/VHDL/Syntax.hs:1755)
    MiscellaneousOperator (src/Language/VHDL/Syntax.hs:1758)
    Literal (src/Language/VHDL/Syntax.hs:1814)
    NumericLiteral (src/Language/VHDL/Syntax.hs:1822)
    Aggregate (src/Language/VHDL/Syntax.hs:1846)
    ElementAssociation (src/Language/VHDL/Syntax.hs:1851)
    Choices (src/Language/VHDL/Syntax.hs:1857)
    Choice (src/Language/VHDL/Syntax.hs:1860)
    FunctionCall (src/Language/VHDL/Syntax.hs:1886)
    ActualParameterPart (src/Language/VHDL/Syntax.hs:1892)
    QualifiedExpression (src/Language/VHDL/Syntax.hs:1902)
    TypeConversion (src/Language/VHDL/Syntax.hs:1913)
    Allocator (src/Language/VHDL/Syntax.hs:1927)
    SequenceOfStatements (src/Language/VHDL/Syntax.hs:1977)
    SequentialStatement (src/Language/VHDL/Syntax.hs:1979)
    WaitStatement (src/Language/VHDL/Syntax.hs:2012)
    SensitivityClause (src/Language/VHDL/Syntax.hs:2016)
    SensitivityList (src/Language/VHDL/Syntax.hs:2019)
    ConditionClause (src/Language/VHDL/Syntax.hs:2022)
    Condition (src/Language/VHDL/Syntax.hs:2025)
    TimeoutClause (src/Language/VHDL/Syntax.hs:2027)
    AssertionStatement (src/Language/VHDL/Syntax.hs:2041)
    Assertion (src/Language/VHDL/Syntax.hs:2045)
    ReportStatement (src/Language/VHDL/Syntax.hs:2058)
    SignalAssignmentStatement (src/Language/VHDL/Syntax.hs:2081)
    DelayMechanism (src/Language/VHDL/Syntax.hs:2085)
    Target (src/Language/VHDL/Syntax.hs:2090)
    Waveform (src/Language/VHDL/Syntax.hs:2095)
    WaveformElement (src/Language/VHDL/Syntax.hs:2108)
    VariableAssignmentStatement (src/Language/VHDL/Syntax.hs:2120)
    ProcedureCallStatement (src/Language/VHDL/Syntax.hs:2137)
    ProcedureCall (src/Language/VHDL/Syntax.hs:2141)
    IfStatement (src/Language/VHDL/Syntax.hs:2159)
    CaseStatement (src/Language/VHDL/Syntax.hs:2182)
    CaseStatementAlternative (src/Language/VHDL/Syntax.hs:2189)
    LoopStatement (src/Language/VHDL/Syntax.hs:2209)
    IterationScheme (src/Language/VHDL/Syntax.hs:2216)
    ParameterSpecification (src/Language/VHDL/Syntax.hs:2221)
    NextStatement (src/Language/VHDL/Syntax.hs:2234)
    ExitStatement (src/Language/VHDL/Syntax.hs:2248)
    ReturnStatement (src/Language/VHDL/Syntax.hs:2262)
    NullStatement (src/Language/VHDL/Syntax.hs:2275)
    ConcurrentStatement (src/Language/VHDL/Syntax.hs:2299)
    BlockStatement (src/Language/VHDL/Syntax.hs:2334)
    BlockHeader (src/Language/VHDL/Syntax.hs:2343)
    BlockDeclarativePart (src/Language/VHDL/Syntax.hs:2349)
    BlockStatementPart (src/Language/VHDL/Syntax.hs:2351)
    ProcessStatement (src/Language/VHDL/Syntax.hs:2385)
    ProcessDeclarativePart (src/Language/VHDL/Syntax.hs:2394)
    ProcessDeclarativeItem (src/Language/VHDL/Syntax.hs:2396)
    ProcessStatementPart (src/Language/VHDL/Syntax.hs:2411)
    ConcurrentProcedureCallStatement (src/Language/VHDL/Syntax.hs:2420)
    ConcurrentAssertionStatement (src/Language/VHDL/Syntax.hs:2434)
    ConcurrentSignalAssignmentStatement (src/Language/VHDL/Syntax.hs:2451)
    Options (src/Language/VHDL/Syntax.hs:2464)
    ConditionalSignalAssignment (src/Language/VHDL/Syntax.hs:2481)
    ConditionalWaveforms (src/Language/VHDL/Syntax.hs:2488)
    SelectedSignalAssignment (src/Language/VHDL/Syntax.hs:2506)
    SelectedWaveforms (src/Language/VHDL/Syntax.hs:2514)
    ComponentInstantiationStatement (src/Language/VHDL/Syntax.hs:2535)
    InstantiatedUnit (src/Language/VHDL/Syntax.hs:2543)
    GenerateStatement (src/Language/VHDL/Syntax.hs:2573)
    GenerationScheme (src/Language/VHDL/Syntax.hs:2581)
    Label (src/Language/VHDL/Syntax.hs:2586)
    UseClause (src/Language/VHDL/Syntax.hs:2612)
    DesignFile (src/Language/VHDL/Syntax.hs:2649)
    DesignUnit (src/Language/VHDL/Syntax.hs:2651)
    LibraryUnit (src/Language/VHDL/Syntax.hs:2654)
    PrimaryUnit (src/Language/VHDL/Syntax.hs:2659)
    SecondaryUnit (src/Language/VHDL/Syntax.hs:2665)
    LibraryClause (src/Language/VHDL/Syntax.hs:2681)
    LogicalNameList (src/Language/VHDL/Syntax.hs:2684)
    LogicalName (src/Language/VHDL/Syntax.hs:2687)
    ContextClause (src/Language/VHDL/Syntax.hs:2700)
    ContextItem (src/Language/VHDL/Syntax.hs:2702)
    Identifier (src/Language/VHDL/Syntax.hs:2736)
    CharacterLiteral (src/Language/VHDL/Syntax.hs:2739)
    StringLiteral (src/Language/VHDL/Syntax.hs:2742)
    AbstractLiteral (src/Language/VHDL/Syntax.hs:2745)
    Base (src/Language/VHDL/Syntax.hs:2750)
    BaseSpecifier (src/Language/VHDL/Syntax.hs:2753)
    BaseUnitDeclaration (src/Language/VHDL/Syntax.hs:2756)
    BasedInteger (src/Language/VHDL/Syntax.hs:2759)
    BasedLiteral (src/Language/VHDL/Syntax.hs:2762)
    BasicCharacter (src/Language/VHDL/Syntax.hs:2765)
    BasicGraphicCharacter (src/Language/VHDL/Syntax.hs:2768)
    BasicIdentifier (src/Language/VHDL/Syntax.hs:2771)
    BitStringLiteral (src/Language/VHDL/Syntax.hs:2774)
    BitValue (src/Language/VHDL/Syntax.hs:2777)
    DecimalLiteral (src/Language/VHDL/Syntax.hs:2780)
    Exponent (src/Language/VHDL/Syntax.hs:2783)
    ExtendedDigit (src/Language/VHDL/Syntax.hs:2786)
    ExtendedIdentifier (src/Language/VHDL/Syntax.hs:2789)
    GraphicCharacter (src/Language/VHDL/Syntax.hs:2792)
    Letter (src/Language/VHDL/Syntax.hs:2795)
    LetterOrDigit (src/Language/VHDL/Syntax.hs:2798)
   0% (  0 /  2) in 'Language.VHDL.Pretty'
  Missing documentation for:
    Module header
    Pretty (src/Language/VHDL/Pretty.hs:13)
  67% (  2 /  3) in 'Language.VHDL'
  Missing documentation for:
    Module header
Documentation created: dist/doc/html/language-vhdl/index.html,
dist/doc/html/language-vhdl/language-vhdl.txt
Creating package registration file:
/tmp/pkgConf-language-vhdl-0.1.22145174067468703135.3
Installing library in
/home/builder/hackage-server/build-cache/tmp-install/lib/x86_64-linux-ghc-7.10.2/language-vhdl-0.1.2.3-C83gf5rhwqX3dJ1VeF4aP8
Registering language-vhdl-0.1.2.3...
Installed language-vhdl-0.1.2.3

Test log

No test log was submitted for this report.