| Safe Haskell | Safe-Inferred |
|---|---|
| Language | Haskell2010 |
Language.Pck.Cpu.Instruction
Contents
- data Inst
- = NOP
- | HALT
- | MOVI GReg Int
- | MOV GReg GReg
- | MOVPC GReg
- | ADD GReg GReg GReg
- | SUB GReg GReg GReg
- | CMP GReg GReg
- | ABS GReg GReg
- | ASH GReg GReg GReg
- | MUL GReg GReg GReg
- | DIV GReg GReg GReg
- | AND GReg GReg GReg
- | OR GReg GReg GReg
- | NOT GReg GReg
- | XOR GReg GReg GReg
- | LSH GReg GReg GReg
- | BRI FCond Int
- | JRI Int
- | J GReg
- | CALL GReg
- | RET
- | LD GReg GReg
- | ST GReg GReg
- | UNDEF
- data GReg
- data FCond
the instruction set type
the instruction definition.
You can create instructions as you like :-)
Operand order is Intel, ARM, MIPS, PowerPC,... order. (opcode dst src1 src2)
Constructors
| NOP | no operation |
| HALT | halt (stop the processor) |
| MOVI GReg Int | GReg <- Int |
| MOV GReg GReg | GReg <- GReg |
| MOVPC GReg | GReg <- PC |
| ADD GReg GReg GReg | GReg <- GReg + GReg |
| SUB GReg GReg GReg | GReg <- GReg - GReg |
| CMP GReg GReg | Flag <- compare(GReg, GReg) |
| ABS GReg GReg | GReg <- abs(GReg) |
| ASH GReg GReg GReg | GReg <- GReg << GReg // arithmetic shift |
| MUL GReg GReg GReg | GReg <- GReg * GReg |
| DIV GReg GReg GReg | GReg <- GReg / GReg |
| AND GReg GReg GReg | GReg <- GReg & GReg |
| OR GReg GReg GReg | GReg <- GReg | GReg |
| NOT GReg GReg | GReg <- ~GReg |
| XOR GReg GReg GReg | GReg <- GReg ^ GReg |
| LSH GReg GReg GReg | GReg <- GReg << GReg // logical shift |
| BRI FCond Int | if (FCond(Flag)) goto (PC + Int) // pc relative addressing |
| JRI Int | goto (PC + Int) // pc relative addressing |
| J GReg | goto GReg // absolute addressing |
| CALL GReg | goto GReg; R0 <- PC // absolute addressing |
| RET | goto R0 |
| LD GReg GReg | GReg <- memory(GReg) |
| ST GReg GReg | memory(GReg) <- GReg |
| UNDEF | undefined |
the general purpose registers.
You can create registers as you like :-)