Build #1 for verilog-0.0.10
| Package | verilog-0.0.10 |
|---|
| Install | BuildFailed |
|---|---|
| Docs | NotTried |
| Tests | NotTried |
| Time submitted | 2015-03-26 02:38:56.856731 UTC |
|---|---|
| Compiler | ghc-7.8.3 |
| OS | linux |
| Arch | x86_64 |
| Dependencies | monadLib-3.7.3, base-4.7.0.1, array-0.5.0.0 |
| Flags | none |
Code Coverage
No Code Coverage was submitted for this report.
Build log
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Resolving dependencies...
Configuring monadLib-3.7.3...
Building monadLib-3.7.3...
Preprocessing library monadLib-3.7.3...
[1 of 3] Compiling MonadLib ( src/MonadLib.hs, dist/build/MonadLib.o )
[2 of 3] Compiling MonadLib.Derive ( src/MonadLib/Derive.hs, dist/build/MonadLib/Derive.o )
[3 of 3] Compiling MonadLib.Monads ( src/MonadLib/Monads.hs, dist/build/MonadLib/Monads.o )
In-place registering monadLib-3.7.3...
Running Haddock for monadLib-3.7.3...
Running hscolour for monadLib-3.7.3...
Preprocessing library monadLib-3.7.3...
Preprocessing library monadLib-3.7.3...
Haddock coverage:
97% ( 62 / 64) in 'MonadLib'
92% ( 24 / 26) in 'MonadLib.Derive'
17% ( 2 / 12) in 'MonadLib.Monads'
Documentation created: dist/doc/html/monadLib/index.html,
dist/doc/html/monadLib/monadLib.txt
Creating package registration file: /tmp/pkgConf-monadLib-3.78194.3
Installing library in
/home/builder/hackage-server/build-cache/tmp-install/lib/x86_64-linux-ghc-7.8.3/monadLib-3.7.3
Registering monadLib-3.7.3...
Installed monadLib-3.7.3
Downloading verilog-0.0.10...
Configuring verilog-0.0.10...
Building verilog-0.0.10...
Preprocessing library verilog-0.0.10...
[1 of 8] Compiling Language.Verilog.Parser.Tokens ( Language/Verilog/Parser/Tokens.hs, dist/build/Language/Verilog/Parser/Tokens.o )
[2 of 8] Compiling Language.Verilog.Parser.Preprocess ( Language/Verilog/Parser/Preprocess.hs, dist/build/Language/Verilog/Parser/Preprocess.o )
[3 of 8] Compiling Language.Verilog.Parser.Lex ( dist/build/Language/Verilog/Parser/Lex.hs, dist/build/Language/Verilog/Parser/Lex.o )
dist/build/Language/Verilog/Parser/Lex.hs:439:17:
Pattern bindings containing unlifted types should use an outermost bang pattern:
((I# (ord_c))) = fromIntegral c
In the expression:
let
(base) = alexIndexInt32OffAddr alex_base s
((I# (ord_c))) = fromIntegral c
(offset) = (base +# ord_c)
....
in
case new_s of {
-1# -> (new_acc, input)
_ -> alex_scan_tkn
user
orig_input
(if c < 128 || c >= 192 then (len +# 1#) else len)
new_input
new_s
new_acc }
In a case alternative:
Just (c, new_input)
-> let
(base) = alexIndexInt32OffAddr alex_base s
((I# (ord_c))) = fromIntegral c
....
in
case new_s of {
-1# -> (new_acc, input)
_ -> alex_scan_tkn
user
orig_input
(if c < 128 || c >= 192 then (len +# 1#) else len)
new_input
new_s
new_acc }
In the second argument of ‘seq’, namely
‘case alexGetByte input of {
Nothing -> (new_acc, input)
Just (c, new_input)
-> let
(base) = ...
....
in
case new_s of {
-1# -> ...
_ -> alex_scan_tkn
user
orig_input
(if c < 128 || c >= 192 then (len +# 1#) else len)
new_input
new_s
new_acc } }’
dist/build/Language/Verilog/Parser/Lex.hs:443:31:
Couldn't match expected type ‘Bool’ with actual type ‘Int#’
In the first argument of ‘(&&)’, namely ‘(offset >=# 0#)’
In the expression: (offset >=# 0#) && (check ==# ord_c)
In the expression:
if (offset >=# 0#) && (check ==# ord_c) then
alexIndexInt16OffAddr alex_table offset
else
alexIndexInt16OffAddr alex_deflt s
dist/build/Language/Verilog/Parser/Lex.hs:443:50:
Couldn't match expected type ‘Bool’ with actual type ‘Int#’
In the second argument of ‘(&&)’, namely ‘(check ==# ord_c)’
In the expression: (offset >=# 0#) && (check ==# ord_c)
In the expression:
if (offset >=# 0#) && (check ==# ord_c) then
alexIndexInt16OffAddr alex_table offset
else
alexIndexInt16OffAddr alex_deflt s
Failed to install verilog-0.0.10
cabal: Error: some packages failed to install:
verilog-0.0.10 failed during the building phase. The exception was:
ExitFailure 1
Test log
No test log was submitted for this report.