Safe Haskell | Safe-Inferred |
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An embedded DSL for Verilog.
- type Verilog a = StateT (Int, a, [ModuleItem]) Id
- elaborate :: String -> a -> Verilog a () -> (a, Module)
- getMeta :: Verilog a a
- setMeta :: a -> Verilog a ()
- genVar :: Verilog a String
- input :: String -> Int -> Verilog a ()
- output :: String -> Int -> Verilog a ()
- wire :: String -> Int -> Maybe Expr -> Verilog a ()
- reg :: String -> Int -> Verilog a ()
- assign :: String -> Expr -> Verilog a ()
- next :: String -> Expr -> Verilog a ()
- var :: String -> Expr
- constant :: Int -> Integer -> Expr
- mappend :: Monoid a => a -> a -> a
- mconcat :: Monoid a => [a] -> a
- (<>) :: Monoid m => m -> m -> m
- mux :: Expr -> Expr -> Expr -> Expr