Language.Verilog.DSL

An embedded DSL for Verilog.

Documentation

type Verilog a = StateT (Int, a, [ModuleItem]) Id

elaborate :: String -> a -> Verilog a () -> (a, Module)

getMeta :: Verilog a a

setMeta :: a -> Verilog a ()

genVar :: Verilog a String

Signal Declarations

input :: String -> Int -> Verilog a ()

output :: String -> Int -> Verilog a ()

wire :: String -> Int -> Maybe Expr -> Verilog a ()

reg :: String -> Int -> Verilog a ()

Module Statements

assign :: LHS -> Expr -> Verilog a ()

inst :: Identifier -> [(Identifier, Expr)] -> Identifier -> [(Identifier, Expr)] -> Verilog a ()

Expressions

var :: String -> Expr

constant :: Int -> Integer -> Expr

mappend :: Monoid a => a -> a -> a

An associative operation

mconcat :: Monoid a => [a] -> a

Fold a list using the monoid. For most types, the default definition for mconcat will be used, but the function is included in the class definition so that an optimized version can be provided for specific types.

(<>) :: Monoid m => m -> m -> m

An infix synonym for mappend.

mux :: Expr -> Expr -> Expr -> Expr

true :: Expr

false :: Expr