Copyright | (c) 2018-2019 Yann Herklotz |
---|---|
License | BSD-3 |
Maintainer | yann [at] yannherklotz [dot] com |
Stability | experimental |
Portability | POSIX |
Safe Haskell | None |
Language | Haskell2010 |
Synopsis
- defaultMain :: IO ()
- data Opts
- = Fuzz {
- fuzzOutput :: !Text
- fuzzConfigFile :: !(Maybe FilePath)
- fuzzForced :: !Bool
- fuzzKeepAll :: !Bool
- fuzzNum :: !Int
- fuzzNoSim :: !Bool
- fuzzNoEquiv :: !Bool
- fuzzNoReduction :: !Bool
- fuzzExistingFile :: !(Maybe FilePath)
- fuzzExistingFileTop :: !Text
- fuzzCrossCheck :: !Bool
- | Generate {
- generateFilename :: !(Maybe FilePath)
- generateConfigFile :: !(Maybe FilePath)
- | Parse {
- parseFilename :: !FilePath
- parseTop :: !Text
- parseOutput :: !(Maybe FilePath)
- parseRemoveConstInConcat :: !Bool
- | Reduce {
- reduceFilename :: !FilePath
- reduceTop :: !Text
- reduceScript :: !(Maybe FilePath)
- reduceSynthesiserDesc :: ![SynthDescription]
- reduceRerun :: !Bool
- | ConfigOpt { }
- = Fuzz {
- data SourceInfo = SourceInfo {}
- runEquivalence :: Maybe Seed -> Gen Verilog -> Text -> Text -> Bool -> Int -> IO ()
- runSimulation :: IO ()
- runReduce :: SourceInfo -> IO SourceInfo
- draw :: IO ()
- procedural :: Text -> Config -> Gen Verilog
- proceduralIO :: Text -> Config -> IO Verilog
- proceduralSrc :: Text -> Config -> Gen SourceInfo
- proceduralSrcIO :: Text -> Config -> IO SourceInfo
- randomMod :: MonadGen m => Int -> Int -> m ModDecl
- module Verismith.Verilog
- module Verismith.Config
- module Verismith.Circuit
- module Verismith.Tool
- module Verismith.Fuzz
- module Verismith.Report
Documentation
defaultMain :: IO () Source #
Types
Fuzz | |
| |
Generate | |
| |
Parse | |
| |
Reduce | |
| |
ConfigOpt | |
|
data SourceInfo Source #
Instances
Run functions
:: Maybe Seed | |
-> Gen Verilog | Generator for the Verilog file. |
-> Text | Name of the folder on each thread. |
-> Text | Name of the general folder being used. |
-> Bool | Keep flag. |
-> Int | Used to track the recursion. |
-> IO () |
Run a fuzz run and check if all of the simulators passed by checking if the generated Verilog files are equivalent.
runSimulation :: IO () Source #
Run a simulation on a random DAG or a random module.
runReduce :: SourceInfo -> IO SourceInfo Source #
Draw a randomly generated DAG to a dot file and compile it to a png so it can be seen.
Verilog generation functions
proceduralSrc :: Text -> Config -> Gen SourceInfo Source #
Given a Text
and a Config
will generate a SourceInfo
which has the
top module set to the right name.
proceduralSrcIO :: Text -> Config -> IO SourceInfo Source #
Sampled and wrapped into a SourceInfo
with the given top module name.
Extra modules
module Verismith.Verilog
module Verismith.Config
module Verismith.Circuit
module Verismith.Tool
module Verismith.Fuzz
module Verismith.Report