Portability | non-portable (Template Haskell) |
---|---|
Stability | experimental |
Maintainer | christiaan.baaij@gmail.com |
A VHDL 93 subset AST (Abstract Syntax Tree), coded so that it can be easy to extend, please see docVHDLvhdl93-syntax.html as reference in order to extend it (this AST is based on that grammar)
- data VHDLId
- fromVHDLId :: VHDLId -> String
- unsafeVHDLBasicId :: String -> VHDLId
- unsafeVHDLExtId :: String -> VHDLId
- mkVHDLBasicId :: String -> EProne VHDLId
- mkVHDLExtId :: String -> EProne VHDLId
- unsafeIdAppend :: VHDLId -> String -> VHDLId
- specialChars :: [Char]
- otherSpecialChars :: [Char]
- reservedWords :: [String]
- data DesignFile = DesignFile [ContextItem] [LibraryUnit]
- data ContextItem
- = Library VHDLId
- | Use SelectedName
- data LibraryUnit
- data EntityDec = EntityDec VHDLId [IfaceSigDec]
- data IfaceSigDec = IfaceSigDec VHDLId Mode TypeMark
- type TypeMark = SimpleName
- data Mode
- data ArchBody = ArchBody VHDLId VHDLName [BlockDecItem] [ConcSm]
- data PackageDec = PackageDec VHDLId [PackageDecItem]
- data PackageDecItem
- = PDITD TypeDec
- | PDISD SubtypeDec
- | PDISS SubProgSpec
- data PackageBody = PackageBody VHDLId [PackageBodyDecItem]
- type PackageBodyDecItem = SubProgBody
- data SubtypeDec = SubtypeDec VHDLId SubtypeIn
- data SubtypeIn = SubtypeIn TypeMark (Maybe SubtypeConstraint)
- type Constraint = IndexConstraint
- data SubtypeConstraint
- data Range
- data IndexConstraint = IndexConstraint [DiscreteRange]
- type DiscreteRange = Range
- data TypeDec = TypeDec VHDLId TypeDef
- data TypeDef
- data ArrayTypeDef
- data RecordTypeDef = RecordTypeDef [ElementDec]
- data ElementDec = ElementDec VHDLId TypeMark
- data EnumTypeDef = EnumTypeDef [VHDLId]
- data IntegerTypeDef = IntegerTypeDef DiscreteRange
- data VHDLName
- type SimpleName = VHDLId
- data SelectedName = Prefix :.: Suffix
- data IndexedName = IndexedName Prefix [Expr]
- type Prefix = VHDLName
- data Suffix
- = SSimple SimpleName
- | All
- data SliceName = SliceName Prefix DiscreteRange
- data AttribName = AttribName Prefix VHDLName (Maybe Expr)
- data BlockDecItem
- = BDISPB SubProgBody
- | BDISD SigDec
- data SubProgBody = SubProgBody SubProgSpec [SubProgDecItem] [SeqSm]
- data SubProgDecItem
- data VarDec = VarDec VHDLId SubtypeIn (Maybe Expr)
- data ConstDec = ConstDec VHDLId SubtypeIn (Maybe Expr)
- data SubProgSpec = Function VHDLId [IfaceVarDec] TypeMark
- data IfaceVarDec = IfaceVarDec VHDLId TypeMark
- data SeqSm
- data ElseIf = ElseIf Expr [SeqSm]
- data Else = Else [SeqSm]
- data CaseSmAlt = CaseSmAlt [Choice] [SeqSm]
- data Choice
- data SigDec = SigDec VHDLId TypeMark (Maybe Expr)
- data ConcSm
- = CSBSm BlockSm
- | CSSASm ConSigAssignSm
- | CSISm CompInsSm
- | CSPSm ProcSm
- | CSGSm GenerateSm
- data BlockSm = BlockSm Label [IfaceSigDec] PMapAspect [BlockDecItem] [ConcSm]
- newtype PMapAspect = PMapAspect [AssocElem]
- type Label = VHDLId
- data AssocElem = (Maybe FormalPart) :=>: ActualPart
- type FormalPart = SimpleName
- type ActualPart = ActualDesig
- data ActualDesig
- data ConSigAssignSm = VHDLName :<==: ConWforms
- data ConWforms = ConWforms [WhenElse] Wform (Maybe When)
- data WhenElse = WhenElse Wform Expr
- newtype When = When Expr
- data Wform
- = Wform [WformElem]
- | Unaffected
- data WformElem = WformElem Expr (Maybe Expr)
- data CompInsSm = CompInsSm Label InsUnit PMapAspect
- data ProcSm = ProcSm Label [SimpleName] [SeqSm]
- data InsUnit = IUEntity VHDLName
- data GenerateSm = GenerateSm Label GenSm [BlockDecItem] [ConcSm]
- data GenSm
- = ForGn VHDLId DiscreteRange
- | IfGn Expr
- data Expr
- = And Expr Expr
- | Or Expr Expr
- | Xor Expr Expr
- | Nand Expr Expr
- | Nor Expr Expr
- | Xnor Expr Expr
- | Expr :=: Expr
- | Expr :/=: Expr
- | Expr :<: Expr
- | Expr :<=: Expr
- | Expr :>: Expr
- | Expr :>=: Expr
- | Sll Expr Expr
- | Srl Expr Expr
- | Sla Expr Expr
- | Sra Expr Expr
- | Rol Expr Expr
- | Ror Expr Expr
- | Expr :+: Expr
- | Expr :-: Expr
- | Expr :&: Expr
- | Neg Expr
- | Pos Expr
- | Expr :*: Expr
- | Expr :/: Expr
- | Mod Expr Expr
- | Rem Expr Expr
- | Expr :**: Expr
- | Abs Expr
- | Not Expr
- | PrimName VHDLName
- | PrimLit Literal
- | PrimFCall FCall
- | Aggregate [ElemAssoc]
- logicalPrec :: Int
- relationalPrec :: Int
- shiftPrec :: Int
- plusPrec :: Int
- signPrec :: Int
- multPrec :: Int
- miscPrec :: Int
- data ElemAssoc = ElemAssoc (Maybe Choice) Expr
- type Literal = String
- data FCall = FCall VHDLName [AssocElem]
Documentation
fromVHDLId :: VHDLId -> StringSource
Obtain the String of a VHDL identifier
unsafeVHDLBasicId :: String -> VHDLIdSource
unsafely create a basic VHDLId (without cheking if the string is correct)
unsafeVHDLExtId :: String -> VHDLIdSource
unsafely create an exteded VHDLId (without cheking if the string is correct)
mkVHDLBasicId :: String -> EProne VHDLIdSource
Create a VHDL basic identifier from a String, previously checking if the String is correct
mkVHDLExtId :: String -> EProne VHDLIdSource
Create a VHDL extended identifier from a String, previously checking if the String is correct. The input string must not include the initial and ending backslashes nad the intermediate backslashes shouldn't be escaped.
unsafeIdAppend :: VHDLId -> String -> VHDLIdSource
Unsafely append a string to a VHDL identifier (i.e. without checking if the resulting identifier is valid)
specialChars :: [Char]Source
special characters as defined in the VHDL93 standard
otherSpecialChars :: [Char]Source
other special characters as defined in the VHDL93 standard
reservedWords :: [String]Source
Reserved identifiers
data LibraryUnit Source
data IfaceSigDec Source
interface_signal_declaration We don't allow the id1,id2,id3 syntax, only one identifier is allowed at once The Mode is mandatory Bus is not allowed Preasigned values are not allowed Subtype indications are not allowed, just a typemark Constraints are not allowed: just add a new type with the constarint in ForSyDe.vhd if it is required
type TypeMark = SimpleNameSource
type_mark We don't distinguish between type names and subtype names We dont' support selected names, only simple names because we won't need name selection (i.e. Use clauses will make name selection unnecesary)
architecture_body [ ARCHITECTURE ] and [ architecture_simple_name ] are not allowed
data PackageDec Source
package_declaration [ PACKAGE ] and [ package_simple_name ] are not allowed
data PackageDecItem Source
package_declarative_item only type declarations, subtype declarations and subprogram specifications (working as subprogram_declaration) allowed
data PackageBody Source
package_body [ PACKAGE ] and [ package_simple_name ] are not allowed
type PackageBodyDecItem = SubProgBodySource
only subprogram_body is allowed
data SubtypeDec Source
subtype-declaration
subtype_indication resolution functions are not permitted
type Constraint = IndexConstraintSource
constraint Only index constraints are allowed
data SubtypeConstraint Source
range the direction must always be "to"
data IndexConstraint Source
index_constraint
type DiscreteRange = RangeSource
discrete_range only ranges are allowed
type_declaration only full_type_declarations are allowed
type_declaration only composite types and enumeration types (a specific scalar type)
data ArrayTypeDef Source
array_type_definition unconstrained_array_definition constrained_array_definition A TypeMark is used instead of a subtype_indication. If subtyping is required, declare a subtype explicitly.
data RecordTypeDef Source
record_type_definition [ record_type_simple_name ] not allowed
data ElementDec Source
element_declaration multi-identifier element declarations not allowed element_subtype_definition is simplified to a type_mark
data EnumTypeDef Source
enumeration_type_definition enumeration literals can only be identifiers
data IntegerTypeDef Source
integer_type_definition integer literals can only be numbers
name operator_names are not allowed
type SimpleName = VHDLIdSource
simple_name
data IndexedName Source
indexed_name note that according to the VHDL93 grammar the index list cannot be empty
suffix no character or operator symbols are accepted
data AttribName Source
attribute_name signatures are not allowed
data BlockDecItem Source
block_declarative_item Only subprogram bodies and signal declarations are allowed
data SubProgBody Source
subprogram_body No subprogram kind nor designator is allowed
data SubProgDecItem Source
subprogram_declarative_item only varaible declarations are allowed.
variable_declaration identifier lists are not allowed
data SubProgSpec Source
subprogram_specification Only Functions are allowed [Pure | Impure] is not allowed Only an identifier is valid as the designator In the formal parameter list only variable declarations are accepted
data IfaceVarDec Source
interface_variable_declaration [variable] is not allowed We don't allow the id1,id2,id3 syntax, only one identifier is allowed Mode is not allowed Resolution functions and constraints are not allowed, thus a TypeMark is used instead of a subtype_indication. If subtyping is required, declare a subtype explicitly.
sequential_statement
Only If, case, return, for loops, assignment, wait for
procedure calls
allowed.
Only for loops are allowed (thus loop_statement doesn't exist) and cannot
be provided labels.
The target cannot be an aggregate.
General wait statements are not allowed, only wait for
It is incorrect to have an empty [CaseSmAlt]
helper type, they doesn't exist in the origianl grammar
helper type, it doesn't exist in the origianl grammar
case_statement_alternative it is incorrect to have an empty [Choice]
choice although any expression is allowed the grammar specfically only allows simple_expressions (not covered in this AST)
signal_declaration We don't allow the id1,id2,id3 syntax, only one identifier is allowed at once Resolution functions and constraints are not allowed, thus a TypeMark is used instead of a subtype_indication Signal kinds are not allowed
concurrent_statement only block statements, component instantiations and signal assignments are allowed
block_statement Generics are not supported The port_clause (with only signals) and port_map_aspect are mandatory The ending [ block_label ] is not allowed
association_element
type FormalPart = SimpleNameSource
formal_part We only accept a formal_designator (which is a name after all), in the forme of simple name (no need for selected names) function_name ( formal_designator ) and type_mark ( formal_designator ) are not allowed
type ActualPart = ActualDesigSource
actual_part We only accept an actual_designator, function_name ( actual_designator ) and type_mark ( actual_designator ) are not allowed
data ActualDesig Source
actual_designator
data ConSigAssignSm Source
concurrent_signal_assignment_statement Only conditional_signal_assignment is allowed (without options) The LHS (targets) are simply signal names, no aggregates
conditional_waveforms
Helper type, it doesn't exist in the VHDL grammar
waveform although it is possible to leave [Expr] empty, that's obviously not valid VHDL waveform
waveform_element Null is not accepted
component_instantiation_statement No generics supported The port map aspect is mandatory
process_statement The label is mandatory Only simple names are accepted in the sensitivity list No declarative part is allowed
ProcSm Label [SimpleName] [SeqSm] |
instantiated_unit Only Entities are allowed and their architecture cannot be specified
expression, instead of creating an AST like the grammar (see commented section below) we made our own expressions which are easier to handle, but which don't don't show operand precedence (that is a responsibility of the pretty printer)
Logical Operators precedence
Relational Operators Precedence
element_association only one choice is allowed
literal Literals are expressed as a string (remember we are generating code, not parsing)