-- | Not exported by default because many of these have the same
--   names as in "Control.Arrow"

{-# LANGUAGE NoMonomorphismRestriction #-}
{-# LANGUAGE ExtendedDefaultRules #-}

module Vivid.ByteBeat (
     (&&&)
   , (|||)
   , (>>>)
   , (<<<)
     -- Reexported from Vivid.UGens.Algebraic:
   , xor

   , byteBeatFromHelpFile
   , baseThing
   ) where


import Vivid.SynthDef
-- import Vivid.SynthDef.ToSig
import Vivid.UGens.Algebraic
import Vivid.UGens.Args
import Vivid.UGens.Generators.Deterministic (impulse)
import Vivid.UGens.Triggers (pulseCount)

(&&&), (|||), (>>>), (<<<)
   :: (ToSig s0 a, ToSig s1 a) => s0 -> s1 -> SDBody' a Signal
-- | Bitwise @and@
&&& :: s0 -> s1 -> SDBody' a Signal
(&&&) = BinaryOp -> s0 -> s1 -> SDBody' a Signal
forall s0 (a :: [Symbol]) s1.
(ToSig s0 a, ToSig s1 a) =>
BinaryOp -> s0 -> s1 -> SDBody' a Signal
biOp BinaryOp
BitAnd
-- | Bitwise @or@
||| :: s0 -> s1 -> SDBody' a Signal
(|||) = BinaryOp -> s0 -> s1 -> SDBody' a Signal
forall s0 (a :: [Symbol]) s1.
(ToSig s0 a, ToSig s1 a) =>
BinaryOp -> s0 -> s1 -> SDBody' a Signal
biOp BinaryOp
BitOr
-- | Bit shift right
>>> :: s0 -> s1 -> SDBody' a Signal
(>>>) = BinaryOp -> s0 -> s1 -> SDBody' a Signal
forall s0 (a :: [Symbol]) s1.
(ToSig s0 a, ToSig s1 a) =>
BinaryOp -> s0 -> s1 -> SDBody' a Signal
biOp BinaryOp
ShiftRight
-- | Bit shift left
<<< :: s0 -> s1 -> SDBody' a Signal
(<<<) = BinaryOp -> s0 -> s1 -> SDBody' a Signal
forall s0 (a :: [Symbol]) s1.
(ToSig s0 a, ToSig s1 a) =>
BinaryOp -> s0 -> s1 -> SDBody' a Signal
biOp BinaryOp
ShiftLeft
-- Also 'xor' from Vivid.UGens.Algebraic


-- | E.g.
-- 
--   > play byteBeatFromHelpFile
byteBeatFromHelpFile :: SDBody' a Signal
byteBeatFromHelpFile :: SDBody' a Signal
byteBeatFromHelpFile = (Signal -> SDBody' a Signal) -> SDBody' a Signal
forall (a :: [Symbol]).
(Signal -> SDBody' a Signal) -> SDBody' a Signal
baseThing ((Signal -> SDBody' a Signal) -> SDBody' a Signal)
-> (Signal -> SDBody' a Signal) -> SDBody' a Signal
forall a b. (a -> b) -> a -> b
$ \Signal
t ->
   (((Signal
t Signal -> Integer -> SDBody' a Signal
forall i0 (a :: [Symbol]) i1.
(ToSig i0 a, ToSig i1 a) =>
i0 -> i1 -> SDBody' a Signal
~* Integer
15) SDBody' a Signal -> SDBody' a Signal -> SDBody' a Signal
forall i0 (a :: [Symbol]) i1.
(ToSig i0 a, ToSig i1 a) =>
i0 -> i1 -> SDBody' a Signal
&&& (Signal
t Signal -> Integer -> SDBody' a Signal
forall i0 (a :: [Symbol]) i1.
(ToSig i0 a, ToSig i1 a) =>
i0 -> i1 -> SDBody' a Signal
>>> Integer
5)) SDBody' a Signal -> SDBody' a Signal -> SDBody' a Signal
forall i0 (a :: [Symbol]) i1.
(ToSig i0 a, ToSig i1 a) =>
i0 -> i1 -> SDBody' a Signal
|||
    ((Signal
t Signal -> Integer -> SDBody' a Signal
forall i0 (a :: [Symbol]) i1.
(ToSig i0 a, ToSig i1 a) =>
i0 -> i1 -> SDBody' a Signal
~* Integer
5)  SDBody' a Signal -> SDBody' a Signal -> SDBody' a Signal
forall i0 (a :: [Symbol]) i1.
(ToSig i0 a, ToSig i1 a) =>
i0 -> i1 -> SDBody' a Signal
&&& (Signal
t Signal -> Integer -> SDBody' a Signal
forall i0 (a :: [Symbol]) i1.
(ToSig i0 a, ToSig i1 a) =>
i0 -> i1 -> SDBody' a Signal
>>> Integer
3)) SDBody' a Signal -> SDBody' a Signal -> SDBody' a Signal
forall i0 (a :: [Symbol]) i1.
(ToSig i0 a, ToSig i1 a) =>
i0 -> i1 -> SDBody' a Signal
|||
    ((Signal
t Signal -> Integer -> SDBody' a Signal
forall i0 (a :: [Symbol]) i1.
(ToSig i0 a, ToSig i1 a) =>
i0 -> i1 -> SDBody' a Signal
~* Integer
2)  SDBody' a Signal -> SDBody' a Signal -> SDBody' a Signal
forall i0 (a :: [Symbol]) i1.
(ToSig i0 a, ToSig i1 a) =>
i0 -> i1 -> SDBody' a Signal
&&& (Signal
t Signal -> Integer -> SDBody' a Signal
forall i0 (a :: [Symbol]) i1.
(ToSig i0 a, ToSig i1 a) =>
i0 -> i1 -> SDBody' a Signal
>>> Integer
9)) SDBody' a Signal -> SDBody' a Signal -> SDBody' a Signal
forall i0 (a :: [Symbol]) i1.
(ToSig i0 a, ToSig i1 a) =>
i0 -> i1 -> SDBody' a Signal
|||
    ((Signal
t Signal -> Integer -> SDBody' a Signal
forall i0 (a :: [Symbol]) i1.
(ToSig i0 a, ToSig i1 a) =>
i0 -> i1 -> SDBody' a Signal
~* Integer
8)  SDBody' a Signal -> SDBody' a Signal -> SDBody' a Signal
forall i0 (a :: [Symbol]) i1.
(ToSig i0 a, ToSig i1 a) =>
i0 -> i1 -> SDBody' a Signal
&&& (Signal
t Signal -> Integer -> SDBody' a Signal
forall i0 (a :: [Symbol]) i1.
(ToSig i0 a, ToSig i1 a) =>
i0 -> i1 -> SDBody' a Signal
>>> Integer
11)))
   SDBody' a Signal -> Integer -> SDBody' a Signal
forall i0 (a :: [Symbol]) i1.
(ToSig i0 a, ToSig i1 a) =>
i0 -> i1 -> SDBody' a Signal
~- Integer
3

-- | E.g.
-- 
--   > play $ baseThing $ \t -> t &&& (t >>> 8)
baseThing :: (Signal -> SDBody' a Signal) -> SDBody' a Signal
baseThing :: (Signal -> SDBody' a Signal) -> SDBody' a Signal
baseThing Signal -> SDBody' a Signal
f = do
   Signal
t <- UA "trigger" a -> SDBody (UA "trigger" a) Signal
forall a. Args '[] '["trigger", "reset"] a => a -> SDBody a Signal
pulseCount (SDBody' a Signal -> UA "trigger" a
forall s (as :: [Symbol]). ToSig s as => s -> UA "trigger" as
trig_ (SDBody' a Signal -> UA "trigger" a)
-> SDBody' a Signal -> UA "trigger" a
forall a b. (a -> b) -> a -> b
$ UA "freq" a -> SDBody (UA "freq" a) Signal
forall a. Args '["freq"] '["phase"] a => a -> SDBody a Signal
impulse (Double -> UA "freq" a
forall s (as :: [Symbol]). ToSig s as => s -> UA "freq" as
freq_ Double
8e3))
   Signal
sig0 <- Signal -> SDBody' a Signal
f Signal
t
   Signal
sig1 <- BinaryOp -> Signal -> Integer -> SDBody' a Signal
forall s0 (a :: [Symbol]) s1.
(ToSig s0 a, ToSig s1 a) =>
BinaryOp -> s0 -> s1 -> SDBody' a Signal
biOp BinaryOp
Mod Signal
sig0 Integer
256
   ((Signal
sig1 Signal -> Integer -> SDBody' a Signal
forall i0 (a :: [Symbol]) i1.
(ToSig i0 a, ToSig i1 a) =>
i0 -> i1 -> SDBody' a Signal
~/ Integer
127) SDBody' a Signal -> Integer -> SDBody' a Signal
forall i0 (a :: [Symbol]) i1.
(ToSig i0 a, ToSig i1 a) =>
i0 -> i1 -> SDBody' a Signal
~- Integer
1) SDBody' a Signal -> Double -> SDBody' a Signal
forall i0 (a :: [Symbol]) i1.
(ToSig i0 a, ToSig i1 a) =>
i0 -> i1 -> SDBody' a Signal
~* Double
0.1