Xilinx Lava is a library for FPGA circuit design with a focus on circuit layout.
- inv :: Bit -> Out Bit
- and2 :: (Bit, Bit) -> Out Bit
- and3 :: (Bit, Bit, Bit) -> Out Bit
- and4 :: (Bit, Bit, Bit, Bit) -> Out Bit
- and5 :: (Bit, Bit, Bit, Bit, Bit) -> Out Bit
- and6 :: (Bit, Bit, Bit, Bit, Bit, Bit) -> Out Bit
- or2 :: (Bit, Bit) -> Out Bit
- or3 :: (Bit, Bit, Bit) -> Out Bit
- or4 :: (Bit, Bit, Bit, Bit) -> Out Bit
- or5 :: (Bit, Bit, Bit, Bit, Bit) -> Out Bit
- or6 :: (Bit, Bit, Bit, Bit, Bit, Bit) -> Out Bit
- nor2 :: (Bit, Bit) -> Out Bit
- xor2 :: (Bit, Bit) -> Out Bit
- xnor2 :: (Bit, Bit) -> Out Bit
- mux :: (Bit, (Bit, Bit)) -> Out Bit
- muxcy :: Bit -> Bit -> Bit -> Out Bit
- muxcy_d :: Bit -> Bit -> Bit -> Out (Bit, Bit)
- muxcy_l :: Bit -> Bit -> Bit -> Out Bit
- muxf5 :: Bit -> Bit -> Bit -> Out Bit
- muxf5_d :: Bit -> Bit -> Bit -> Out (Bit, Bit)
- muxf5_l :: Bit -> Bit -> Bit -> Out Bit
- muxf6 :: Bit -> Bit -> Bit -> Out Bit
- muxf6_d :: Bit -> Bit -> Bit -> Out (Bit, Bit)
- muxf6_l :: Bit -> Bit -> Bit -> Out Bit
- muxf7 :: Bit -> Bit -> Bit -> Out Bit
- muxf7_d :: Bit -> Bit -> Bit -> Out (Bit, Bit)
- muxf7_l :: Bit -> Bit -> Bit -> Out Bit
- muxf8 :: Bit -> Bit -> Bit -> Out Bit
- muxf8_d :: Bit -> Bit -> Bit -> Out (Bit, Bit)
- muxf8_l :: Bit -> Bit -> Bit -> Out Bit
- xorcy :: Bit -> Bit -> Out Bit
- xorcy_d :: Bit -> Bit -> Out (Bit, Bit)
- xorcy_l :: Bit -> Bit -> Out Bit
- fd :: Bit -> Bit -> Out Bit
- fdc :: Bit -> Bit -> Bit -> Out Bit
- fdc_1 :: Bit -> Bit -> Bit -> Out Bit
- fdce :: Bit -> Bit -> Bit -> Bit -> Out Bit
- fdce_1 :: Bit -> Bit -> Bit -> Bit -> Out Bit
- fdcp :: Bit -> Bit -> Bit -> Bit -> Out Bit
- fdcpe :: Bit -> Bit -> Bit -> Bit -> Bit -> Out Bit
- fdcpe_1 :: Bit -> Bit -> Bit -> Bit -> Bit -> Out Bit
- srl16e :: Bit -> Bit -> Bit -> Bit -> Bit -> Bit -> Bit -> Out Bit
- and2b1l :: Bit -> Bit -> Out Bit
- or2l :: Bit -> Bit -> Out Bit
- ibufg :: Bit -> Out Bit
- bufg :: Bit -> Out Bit
- bufgp :: Bit -> Out Bit
- obufg :: Bit -> Out Bit
- obufds :: Bit -> Out (Bit, Bit)
- (>->) :: (a -> Out b) -> (b -> Out c) -> a -> Out c
- (>|>) :: (a -> Out b) -> (b -> Out c) -> a -> Out c
- replicateHorizontal :: Int -> (a -> Out a) -> a -> Out a
- par2 :: (a -> Out c) -> (b -> Out d) -> (a, b) -> Out (c, d)
- hpar :: [a -> Out b] -> [a] -> Out [b]
- hparN :: Int -> (a -> Out b) -> [a] -> Out [b]
- fork2 :: a -> Out (a, a)
- listToPair :: [a] -> Out (a, a)
- pairToList :: (a, a) -> Out [a]
- ziP :: ([a], [b]) -> Out [(a, b)]
- unziP :: [(a, b)] -> Out ([a], [b])
- zipList :: [[a]] -> Out [[a]]
- unzipList :: [[a]] -> Out [[a]]
- fstListPair :: [a] -> a
- sndListPair :: [a] -> a
- pair :: [a] -> Out [[a]]
- unpair :: [[a]] -> Out [a]
- halve :: [a] -> Out ([a], [a])
- unhalve :: ([a], [a]) -> Out [a]
- halveList :: [a] -> Out [[a]]
- unhalveList :: [[a]] -> Out [a]
- chop :: Int -> [a] -> Out [[a]]
- concaT :: [[a]] -> Out [a]
- fstList :: ([a] -> Out [a]) -> [a] -> Out [a]
- sndList :: ([a] -> Out [a]) -> [a] -> Out [a]
- fsT :: (a -> Out b) -> (a, c) -> Out (b, c)
- snD :: (b -> Out c) -> (a, b) -> Out (a, c)
- reversE :: [a] -> Out [a]
- inputPort :: String -> NetType -> Out Bit
- inputBitVec :: String -> NetType -> Out [Bit]
- outputPort :: String -> NetType -> Bit -> Out ()
- outputBitVec :: String -> NetType -> [Bit] -> Out ()
- data Dir
- data NetType
- data Netlist
- type Out a = State Netlist a
- type Bit = Int
- data XilinxArchitecture
- computeNetlist :: XilinxArchitecture -> Out () -> Netlist
- putXilinxVHDL :: String -> Netlist -> IO ()
- primitiveGate :: String -> [(String, Bit)] -> [String] -> Maybe (Int, Int) -> Out [Bit]
- lavaVersion :: (Int, Int, Int, Int)
Lava Gates
LUT-based gates
The inv
function implements an invertor explicitly with a LUT1.
The and2
function implements an AND gate explicitly with a LUT2.
The and3
function implements an AND gate explicitly with a LUT3.
The and4
function implements an AND gate explicitly with a LUT4.
The and5
function implements an AND gate explicitly with a LUT5.
The and6
function implements an AND gate explicitly with a LUT6.
The or2
function implements an OR gate explicitly with a LUT2.
The or3
function implements an AND gate explicitly with a LUT3.
The or4
function implements an AND gate explicitly with a LUT4.
The or5
function implements an AND gate explicitly with a LUT5.
The and6
function implements an AND gate explicitly with a LUT6.
The nor2
function implements an NOR gate explicitly with a LUT2.
The xor2
function implements an XOR gate explicitly with a LUT2.
The xnor2
function implements an XOR gate explicitly with a LUT2.
A multiplexor implemented with a LUT3
Carry-chain elements
Flip-flops
Shift-register primitives
16-bit shift register look-up table with clock enable
Gates implemented in place of a slice latch
Two input and gate implemented in place of a slice latch
Buffers
Double data rate (DDR) components
Lava Combinators
Serial composition combinators
(>->) :: (a -> Out b) -> (b -> Out c) -> a -> Out cSource
Serial composition with horizontal left to right layout
Parallel composition combinators
replicateHorizontal :: Int -> (a -> Out a) -> a -> Out aSource
Repeated serial composition (left to right)
par2 :: (a -> Out c) -> (b -> Out d) -> (a, b) -> Out (c, d)Source
Horizontal parallel composition of two circuits
hparN :: Int -> (a -> Out b) -> [a] -> Out [b]Source
Horizontal repeated parallel composition of a circuit
Wiring combinators
listToPair :: [a] -> Out (a, a)Source
Converts a two element list into a pair
pairToList :: (a, a) -> Out [a]Source
Converts a par into a list containing two elements
zipList :: [[a]] -> Out [[a]]Source
Takes a list containing two elements and returns a list of lists where each element is a two element list
fstListPair :: [a] -> aSource
sndListPair :: [a] -> aSource
halve :: [a] -> Out ([a], [a])Source
Tales a list and returns a pair containing the two halves of the list
unhalveList :: [[a]] -> Out [a]Source
Undoes halveList
Circuit input/output ports
inputBitVec :: String -> NetType -> Out [Bit]Source
inputBitVec
creates a bit-vector input port
outputPort :: String -> NetType -> Bit -> Out ()Source
outputPort
creates a single bit output port
outputBitVec :: String -> NetType -> [Bit] -> Out ()Source
outputBitVec
creates a bit-vector output port
data XilinxArchitecture Source
Generating a Lava netlist
computeNetlist :: XilinxArchitecture -> Out () -> NetlistSource
Adding new primitive gates to the Lava system
:: String | The name of the component |
-> [(String, Bit)] | name of input ports with argument nets |
-> [String] | name of output ports |
-> Maybe (Int, Int) | optional size information for layout |
-> Out [Bit] | a list of output nets from this component |
primitiveGate
adds a primitive gate