The hsverilog package

[Tags:bsd3, library, test]

Synthesizable Verilog DSL supporting for multiple clock and reset


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Properties

Versions 0.1.0
Change log ChangeLog.md
Dependencies base (>=4.6 && <5), containers, shakespeare, text, transformers [details]
License BSD3
Author Junji Hashimoto
Maintainer junji.hashimoto@gmail.com
Stability Experimental
Category Hardware
Bug tracker https://github.com/junjihashimoto/hsverilog/issues
Source repository head: git clone https://github.com/junjihashimoto/hsverilog.git
Uploaded Thu Feb 19 23:59:58 UTC 2015 by junjihashimoto
Distributions NixOS:0.1.0
Downloads 209 total (3 in the last 30 days)
Votes
0 []
Status Docs available [build log]
Last success reported on 2015-05-20 [all 2 reports]

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Readme for hsverilog

Readme for hsverilog-0.1.0

HsVerilog: Synthesizable Verilog DSL supporting for multiple clock and reset

Hackage version Build Status Coverage Status

Getting started

Install this from Hackage.

cabal update && cabal install hsverilog

Usage

Syntax is similar to Verilog. See tests/test.hs and following examples.

counter circuit

circuit "counter" $ do
  clk <- input "clk" Bit
  rstn <- input "rstn" Bit
  _ <- output "dout" $ 7><0
  reg "dout" (7><0) [Posedge clk,Negedge rstn] $ \dout ->
    If (Not (S rstn)) 0 $
      If (Eq dout 7) 
        0
        (dout + 1)