The verilog package
This parser supports a very small subset of Verilog-95. It is intended primarly for machine generated, synthesizable code.
Properties
| Versions | 0.0.0, 0.0.1, 0.0.2 |
|---|---|
| Dependencies | array, base (≥4.0 & <5), polyparse |
| License | BSD3 |
| Author | Tom Hawkins <tomahawkins@gmail.com> |
| Maintainer | Tom Hawkins <tomahawkins@gmail.com> |
| Category | Language, Hardware |
| Home page | http://github.com/tomahawkins/verilog |
| Source repository | git clone git://github.com/tomahawkins/verilog.git |
| Upload date | Wed Nov 16 02:58:55 UTC 2011 |
| Uploaded by | TomHawkins |
| Built on | ghc-7.2 |
Modules
Downloads
- verilog-0.0.2.tar.gz (Cabal source package)
- package description (included in the package)