The verilog package

[Tags:bsd3, library]

A parser and supporting a small subset of Verilog. Intended for machine generated, synthesizable code.

Properties

Versions 0.0.0, 0.0.1, 0.0.2, 0.0.4, 0.0.5, 0.0.6, 0.0.7, 0.0.8, 0.0.9, 0.0.10, 0.0.11
Dependencies array (>=0.4 && <5.0), base (>=4.0 && <5.0) [details]
License BSD3
Author Tom Hawkins <tomahawkins@gmail.com>
Maintainer Tom Hawkins <tomahawkins@gmail.com>
Stability Unknown
Category Language, Hardware, Embedded
Home page http://github.com/tomahawkins/verilog
Source repository head: git clone git://github.com/tomahawkins/verilog.git
Uploaded Thu Mar 26 18:06:06 UTC 2015 by TomHawkins
Distributions NixOS:0.0.11
Downloads 1819 total (28 in the last 30 days)
Votes
0 []
Status Docs not available [build log]
All reported builds failed as of 2015-11-14 [all 5 reports]

Modules

  • Data
    • Data.BitVec
  • Language
    • Language.Verilog
      • Language.Verilog.AST
      • Language.Verilog.Parser
        • Language.Verilog.Parser.Lex
        • Language.Verilog.Parser.Parse
        • Language.Verilog.Parser.Preprocess
        • Language.Verilog.Parser.Tokens

Downloads

Maintainer's Corner

For package maintainers and hackage trustees