Wired-0.3: Wire-aware hardware description

Safe HaskellNone

Lava

Synopsis

Documentation

data Signal Source

Identifies a driver in the circuit. A driver is either a primary input or an output pin of a cell.

data Lava lib a Source

Instances

CellLibrary lib => MonadLava lib (Lava lib) 
Monad (Lava lib) 
Functor (Lava lib) 
MonadFix (Lava lib) 
Applicative (Lava lib) 

class (Monad m, CellLibrary lib) => MonadLava lib m | m -> lib whereSource

Methods

toLava :: m a -> Lava lib aSource

Instances

CellLibrary lib => MonadLava lib (Lava lib) 
MonadLava lib m => MonadLava lib (LayoutT s b m) 

type InterpDesignDB lib x = (DesignDB lib, Map Signal x)Source

hasLoop :: MonadLava lib m => m a -> BoolSource

hasCombLoop :: MonadLava lib m => m a -> BoolSource

class Port p s | p -> sSource

Instances

Port Bool Bool 
Port Int Int 
Port () () 
Port Time Time 
Port Signal Signal 
Port p s => Port [p] s 
Port p s => Port (Maybe p) s 
Port (Signal Bool) (Signal Bool) 
(Port p1 s, Port p2 s) => Port (Either p1 p2) s 
(Port p1 s, Port p2 s) => Port (p1, p2) s 
(Port p1 s, Port p2 s, Port p3 s) => Port (p1, p2, p3) s 
(Port p1 s, Port p2 s, Port p3 s, Port p4 s) => Port (p1, p2, p3, p4) s 

class Port p s => PortStruct p s t | p -> s t, s t -> pSource

Instances

PortStruct Bool Bool () 
PortStruct Int Int () 
PortStruct () () () 
PortStruct Time Time () 
PortStruct Signal Signal () 
PortStruct p s t => PortStruct [p] s [t] 
PortStruct p s t => PortStruct (Maybe p) s (Maybe t) 
PortStruct (Signal Bool) (Signal Bool) () 
(PortStruct p1 s t1, PortStruct p2 s t2) => PortStruct (Either p1 p2) s (Either t1 t2) 
(PortStruct p1 s t1, PortStruct p2 s t2) => PortStruct (p1, p2) s (t1, t2) 
(PortStruct p1 s t1, PortStruct p2 s t2, PortStruct p3 s t3) => PortStruct (p1, p2, p3) s (t1, t2, t3) 
(PortStruct p1 s t1, PortStruct p2 s t2, PortStruct p3 s t3, PortStruct p4 s t4) => PortStruct (p1, p2, p3, p4) s (t1, t2, t3, t4) 

class Port p s => PortFixed p s | p -> sSource

Instances

PortFixed Signal Signal 
(PortFixed p1 s, PortFixed p2 s) => PortFixed (p1, p2) s 
(PortFixed p1 s, PortFixed p2 s, PortFixed p3 s) => PortFixed (p1, p2, p3) s 
(PortFixed p1 s, PortFixed p2 s, PortFixed p3 s, PortFixed p4 s) => PortFixed (p1, p2, p3, p4) s 

input :: forall lib m p. (MonadLava lib m, PortFixed p Signal) => m pSource

inputList :: (MonadLava lib m, PortFixed p Signal) => Int -> m [p]Source

label :: (MonadLava lib m, PortStruct p Signal t) => Tag -> p -> m pSource

toLava2000 :: (MonadLava lib m, PortStruct pli (Signal Bool) ti, PortStruct psi Signal ti, PortStruct pso Signal to, PortStruct plo (Signal Bool) to) => (psi -> m pso) -> pli -> ploSource

simulateSeq :: (MonadLava lib m, PortStruct pni Int ti, PortStruct psi Signal ti, PortStruct pso Signal to, PortStruct pno Int to) => (psi -> m pso) -> [pni] -> [pno]Source

simulate :: (MonadLava lib m, PortStruct pni Int ti, PortStruct psi Signal ti, PortStruct pso Signal to, PortStruct pno Int to) => (psi -> m pso) -> pni -> pnoSource

encodeBin :: Int -> Int -> [Int]Source

encodeBin n x

Encodes the number x as a binary number of length n. The resulting list contains only zeroes and ones.

verify :: forall lib m ps. (MonadLava lib m, PortFixed ps Signal) => (ps -> m Signal) -> IO ()Source

depth :: (MonadLava lib m, PortStruct ps Signal t, PortStruct pd Int t) => m ps -> (pd, InterpDesignDB lib Int)Source

fanout :: MonadLava lib m => m a -> InterpDesignDB lib IntSource

size :: MonadLava lib m => m p -> IntSource