lion: RISC-V Core
Lion is a formally verified, 5-stage pipeline RISC-V core. Lion targets the VELDT FPGA development board and is written in Haskell using Clash.
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- lion-0.1.0.0.tar.gz [browse] (Cabal source package)
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| Versions [RSS] | 0.1.0.0, 0.2.0.0, 0.3.0.0, 0.4.0.0, 0.4.0.1 |
|---|---|
| Change log | CHANGELOG.md |
| Dependencies | base (>=4.13 && <4.15), Cabal, clash-prelude (>=1.2.5 && <1.4), generic-monoid (>=0.1 && <0.2), ghc-typelits-extra, ghc-typelits-knownnat, ghc-typelits-natnormalise, ice40-prim (>=0.1 && <0.2), lens, mtl [details] |
| License | BSD-3-Clause |
| Copyright | (c) 2021 David Cox |
| Author | dopamane <standard.semiconductor@gmail.com> |
| Maintainer | dopamane <standard.semiconductor@gmail.com> |
| Category | Hardware |
| Bug tracker | https://github.com/standardsemiconductor/lion/issues |
| Source repo | head: git clone git://github.com/standardsemiconductor/lion.git |
| Uploaded | by dopamane at 2021-02-28T17:41:03Z |
| Distributions | |
| Downloads | 657 total (11 in the last 30 days) |
| Rating | 2.0 (votes: 1) [estimated by Bayesian average] |
| Your Rating | |
| Status | Docs available [build log] Last success reported on 2021-02-28 [all 1 reports] |
Readme for lion-0.1.0.0
[back to package description]Where Lions Roam: RISC-V on the VELDT
Lion is a formally verified, 5-stage pipeline RISC-V core. Lion targets the VELDT FPGA development board and is written in Haskell using Clash.
This repository contains three parts:
- The Lion library: a pipelined RISC-V core.
- lion-formal: formally verify the core using riscv-formal.
- lion-soc: a System-on-Chip demonstrating usage of the Lion core on the VELDT.
Lion library
Usage:
- Add
lionto build depends section of Cabal file - import module in source files
import Lion.Core
When connecting the core to memory and peripherals, ensure single cycle latency.
Features
Current Support
Architecture: RV32I (no FENCE, ECALL, EBREAK) -- Default configuration
Future Support
All features will be added in a configurable manner extending the default configuration noted above
- Zicsr, Control and Status Register (CSR) Instructions
- CSR registers
- RV32IM
- Hard IP ALU