Language.Verilog.Types

Documentation

type Identifier = String

data Module

Constructors

Module Identifier [Identifier] [ModuleItem]

Instances

Eq Module

Show Module

data ModuleItem

Constructors

Paremeter (Maybe Range) Identifier Expr

Input (Maybe Range) [(Identifier, Maybe Range)]

Output (Maybe Range) [(Identifier, Maybe Range)]

Inout (Maybe Range) [(Identifier, Maybe Range)]

Wire (Maybe Range) [(Identifier, Maybe Range)]

Reg (Maybe Range) [(Identifier, Maybe Range)]

Initial Stmt

Always Sense Stmt

Assign LHS Expr

Instance Identifier [(Identifier, Maybe Expr)] Identifier [(Identifier, Maybe Expr)]

Instances

Eq ModuleItem

Show ModuleItem

data Stmt

Constructors

Block (Maybe Identifier) [Stmt]

Integer Identifier

Case Expr [Case] (Maybe Stmt)

BlockingAssignment LHS Expr

NonBlockingAssignment LHS Expr

For (Identifier, Expr) Expr (Identifier, Expr) Stmt

If Expr Stmt Stmt

StmtCall Call

Delay String Stmt

Null

Instances

Eq Stmt

Show Stmt

data Expr

Constructors

String String

Number String

ExprLHS LHS

ExprCall Call

Not Expr

And Expr Expr

Or Expr Expr

BWNot Expr

BWAnd Expr Expr

BWXor Expr Expr

BWOr Expr Expr

Mul Expr Expr

Div Expr Expr

Mod Expr Expr

Add Expr Expr

Sub Expr Expr

ShiftL Expr Expr

ShiftR Expr Expr

Eq Expr Expr

Ne Expr Expr

Lt Expr Expr

Le Expr Expr

Gt Expr Expr

Ge Expr Expr

Mux Expr Expr Expr

Repeat Expr [Expr]

Concat [Expr]

Instances

Eq Expr

Show Expr

data Sense

Constructors

Sense LHS

SenseOr Sense Sense

SensePosedge LHS

SenseNegedge LHS

Instances

Eq Sense

Show Sense

data LHS

Constructors

LHS Identifier

LHSBit Identifier Expr

LHSRange Identifier Range

Instances

Eq LHS

Show LHS

data Call

Constructors

Call Identifier [Expr]

Instances

Eq Call

Show Call

type Case = ([Expr], Stmt)

type Range = (Expr, Expr)