verilog: A Verilog parser.
This parser supports a very small subset of Verilog-95. It is intended primarly for machine generated, synthesizable code.
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[Index]
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- verilog-0.0.1.tar.gz [browse] (Cabal source package)
- Package description (as included in the package)
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| Versions [RSS] | 0.0.0, 0.0.1, 0.0.2, 0.0.4, 0.0.5, 0.0.6, 0.0.7, 0.0.8, 0.0.9, 0.0.10, 0.0.11 |
|---|---|
| Dependencies | array, base (>=4.0 && <5), polyparse [details] |
| License | BSD-3-Clause |
| Author | Tom Hawkins <tomahawkins@gmail.com> |
| Maintainer | Tom Hawkins <tomahawkins@gmail.com> |
| Category | Language, Hardware |
| Home page | http://github.com/tomahawkins/verilog |
| Source repo | head: git clone git://github.com/tomahawkins/verilog.git |
| Uploaded | by TomHawkins at 2011-11-14T23:03:32Z |
| Distributions | |
| Reverse Dependencies | 1 direct, 0 indirect [details] |
| Downloads | 7625 total (36 in the last 30 days) |
| Rating | (no votes yet) [estimated by Bayesian average] |
| Your Rating | |
| Status | Docs uploaded by user Build status unknown [no reports yet] |