Add | Language.Verilog.Types, Language.Verilog |
alexScanTokens | Language.Verilog.Lex |
Always | Language.Verilog.Types, Language.Verilog |
And | Language.Verilog.Types, Language.Verilog |
Assign | Language.Verilog.Types, Language.Verilog |
Block | Language.Verilog.Types, Language.Verilog |
BlockingAssignment | Language.Verilog.Types, Language.Verilog |
BWAnd | Language.Verilog.Types, Language.Verilog |
BWNot | Language.Verilog.Types, Language.Verilog |
BWOr | Language.Verilog.Types, Language.Verilog |
BWXor | Language.Verilog.Types, Language.Verilog |
Call | |
1 (Type/Class) | Language.Verilog.Types, Language.Verilog |
2 (Data Constructor) | Language.Verilog.Types, Language.Verilog |
Case | |
1 (Type/Class) | Language.Verilog.Types, Language.Verilog |
2 (Data Constructor) | Language.Verilog.Types, Language.Verilog |
Concat | Language.Verilog.Types, Language.Verilog |
Delay | Language.Verilog.Types, Language.Verilog |
Div | Language.Verilog.Types, Language.Verilog |
Eq | Language.Verilog.Types, Language.Verilog |
Expr | Language.Verilog.Types, Language.Verilog |
ExprCall | Language.Verilog.Types, Language.Verilog |
ExprLHS | Language.Verilog.Types, Language.Verilog |
For | Language.Verilog.Types, Language.Verilog |
Ge | Language.Verilog.Types, Language.Verilog |
Gt | Language.Verilog.Types, Language.Verilog |
Identifier | Language.Verilog.Types, Language.Verilog |
Id_escaped | Language.Verilog.Tokens |
Id_simple | Language.Verilog.Tokens |
Id_system | Language.Verilog.Tokens |
If | Language.Verilog.Types, Language.Verilog |
Initial | Language.Verilog.Types, Language.Verilog |
Inout | Language.Verilog.Types, Language.Verilog |
Input | Language.Verilog.Types, Language.Verilog |
Instance | Language.Verilog.Types, Language.Verilog |
Integer | Language.Verilog.Types, Language.Verilog |
KW_alias | Language.Verilog.Tokens |
KW_always | Language.Verilog.Tokens |
KW_always_comb | Language.Verilog.Tokens |
KW_always_ff | Language.Verilog.Tokens |
KW_always_latch | Language.Verilog.Tokens |
KW_and | Language.Verilog.Tokens |
KW_assert | Language.Verilog.Tokens |
KW_assign | Language.Verilog.Tokens |
KW_assume | Language.Verilog.Tokens |
KW_automatic | Language.Verilog.Tokens |
KW_before | Language.Verilog.Tokens |
KW_begin | Language.Verilog.Tokens |
KW_bind | Language.Verilog.Tokens |
KW_bins | Language.Verilog.Tokens |
KW_binsof | Language.Verilog.Tokens |
KW_bit | Language.Verilog.Tokens |
KW_break | Language.Verilog.Tokens |
KW_buf | Language.Verilog.Tokens |
KW_bufif0 | Language.Verilog.Tokens |
KW_bufif1 | Language.Verilog.Tokens |
KW_byte | Language.Verilog.Tokens |
KW_case | Language.Verilog.Tokens |
KW_casex | Language.Verilog.Tokens |
KW_casez | Language.Verilog.Tokens |
KW_cell | Language.Verilog.Tokens |
KW_chandle | Language.Verilog.Tokens |
KW_class | Language.Verilog.Tokens |
KW_clocking | Language.Verilog.Tokens |
KW_cmos | Language.Verilog.Tokens |
KW_config | Language.Verilog.Tokens |
KW_const | Language.Verilog.Tokens |
KW_constraint | Language.Verilog.Tokens |
KW_context | Language.Verilog.Tokens |
KW_continue | Language.Verilog.Tokens |
KW_cover | Language.Verilog.Tokens |
KW_covergroup | Language.Verilog.Tokens |
KW_coverpoint | Language.Verilog.Tokens |
KW_cross | Language.Verilog.Tokens |
KW_deassign | Language.Verilog.Tokens |
KW_default | Language.Verilog.Tokens |
KW_defparam | Language.Verilog.Tokens |
KW_design | Language.Verilog.Tokens |
KW_disable | Language.Verilog.Tokens |
KW_dist | Language.Verilog.Tokens |
KW_do | Language.Verilog.Tokens |
KW_edge | Language.Verilog.Tokens |
KW_else | Language.Verilog.Tokens |
KW_end | Language.Verilog.Tokens |
KW_endcase | Language.Verilog.Tokens |
KW_endclass | Language.Verilog.Tokens |
KW_endclocking | Language.Verilog.Tokens |
KW_endconfig | Language.Verilog.Tokens |
KW_endfunction | Language.Verilog.Tokens |
KW_endgenerate | Language.Verilog.Tokens |
KW_endgroup | Language.Verilog.Tokens |
KW_endinterface | Language.Verilog.Tokens |
KW_endmodule | Language.Verilog.Tokens |
KW_endpackage | Language.Verilog.Tokens |
KW_endprimitive | Language.Verilog.Tokens |
KW_endprogram | Language.Verilog.Tokens |
KW_endproperty | Language.Verilog.Tokens |
KW_endsequence | Language.Verilog.Tokens |
KW_endspecify | Language.Verilog.Tokens |
KW_endtable | Language.Verilog.Tokens |
KW_endtask | Language.Verilog.Tokens |
KW_enum | Language.Verilog.Tokens |
KW_event | Language.Verilog.Tokens |
KW_expect | Language.Verilog.Tokens |
KW_export | Language.Verilog.Tokens |
KW_extends | Language.Verilog.Tokens |
KW_extern | Language.Verilog.Tokens |
KW_final | Language.Verilog.Tokens |
KW_first_match | Language.Verilog.Tokens |
KW_for | Language.Verilog.Tokens |
KW_force | Language.Verilog.Tokens |
KW_foreach | Language.Verilog.Tokens |
KW_forever | Language.Verilog.Tokens |
KW_fork | Language.Verilog.Tokens |
KW_forkjoin | Language.Verilog.Tokens |
KW_function | Language.Verilog.Tokens |
KW_function_prototype | Language.Verilog.Tokens |
KW_generate | Language.Verilog.Tokens |
KW_genvar | Language.Verilog.Tokens |
KW_highz0 | Language.Verilog.Tokens |
KW_highz1 | Language.Verilog.Tokens |
KW_if | Language.Verilog.Tokens |
KW_iff | Language.Verilog.Tokens |
KW_ifnone | Language.Verilog.Tokens |
KW_ignore_bins | Language.Verilog.Tokens |
KW_illegal_bins | Language.Verilog.Tokens |
KW_import | Language.Verilog.Tokens |
KW_incdir | Language.Verilog.Tokens |
KW_include | Language.Verilog.Tokens |
KW_initial | Language.Verilog.Tokens |
KW_inout | Language.Verilog.Tokens |
KW_input | Language.Verilog.Tokens |
KW_inside | Language.Verilog.Tokens |
KW_instance | Language.Verilog.Tokens |
KW_int | Language.Verilog.Tokens |
KW_integer | Language.Verilog.Tokens |
KW_interface | Language.Verilog.Tokens |
KW_intersect | Language.Verilog.Tokens |
KW_join | Language.Verilog.Tokens |
KW_join_any | Language.Verilog.Tokens |
KW_join_none | Language.Verilog.Tokens |
KW_large | Language.Verilog.Tokens |
KW_liblist | Language.Verilog.Tokens |
KW_library | Language.Verilog.Tokens |
KW_local | Language.Verilog.Tokens |
KW_localparam | Language.Verilog.Tokens |
KW_logic | Language.Verilog.Tokens |
KW_longint | Language.Verilog.Tokens |
KW_macromodule | Language.Verilog.Tokens |
KW_matches | Language.Verilog.Tokens |
KW_medium | Language.Verilog.Tokens |
KW_modport | Language.Verilog.Tokens |
KW_module | Language.Verilog.Tokens |
KW_nand | Language.Verilog.Tokens |
KW_negedge | Language.Verilog.Tokens |
KW_new | Language.Verilog.Tokens |
KW_nmos | Language.Verilog.Tokens |
KW_nor | Language.Verilog.Tokens |
KW_noshowcancelled | Language.Verilog.Tokens |
KW_not | Language.Verilog.Tokens |
KW_notif0 | Language.Verilog.Tokens |
KW_notif1 | Language.Verilog.Tokens |
KW_null | Language.Verilog.Tokens |
KW_option | Language.Verilog.Tokens |
KW_or | Language.Verilog.Tokens |
KW_output | Language.Verilog.Tokens |
KW_package | Language.Verilog.Tokens |
KW_packed | Language.Verilog.Tokens |
KW_parameter | Language.Verilog.Tokens |
KW_pathpulse_dollar | Language.Verilog.Tokens |
KW_pmos | Language.Verilog.Tokens |
KW_posedge | Language.Verilog.Tokens |
KW_primitive | Language.Verilog.Tokens |
KW_priority | Language.Verilog.Tokens |
KW_program | Language.Verilog.Tokens |
KW_property | Language.Verilog.Tokens |
KW_protected | Language.Verilog.Tokens |
KW_pull0 | Language.Verilog.Tokens |
KW_pull1 | Language.Verilog.Tokens |
KW_pulldown | Language.Verilog.Tokens |
KW_pullup | Language.Verilog.Tokens |
KW_pulsestyle_ondetect | Language.Verilog.Tokens |
KW_pulsestyle_onevent | Language.Verilog.Tokens |
KW_pure | Language.Verilog.Tokens |
KW_rand | Language.Verilog.Tokens |
KW_randc | Language.Verilog.Tokens |
KW_randcase | Language.Verilog.Tokens |
KW_randsequence | Language.Verilog.Tokens |
KW_rcmos | Language.Verilog.Tokens |
KW_real | Language.Verilog.Tokens |
KW_realtime | Language.Verilog.Tokens |
KW_ref | Language.Verilog.Tokens |
KW_reg | Language.Verilog.Tokens |
KW_release | Language.Verilog.Tokens |
KW_repeat | Language.Verilog.Tokens |
KW_return | Language.Verilog.Tokens |
KW_rnmos | Language.Verilog.Tokens |
KW_rpmos | Language.Verilog.Tokens |
KW_rtran | Language.Verilog.Tokens |
KW_rtranif0 | Language.Verilog.Tokens |
KW_rtranif1 | Language.Verilog.Tokens |
KW_scalared | Language.Verilog.Tokens |
KW_sequence | Language.Verilog.Tokens |
KW_shortint | Language.Verilog.Tokens |
KW_shortreal | Language.Verilog.Tokens |
KW_showcancelled | Language.Verilog.Tokens |
KW_signed | Language.Verilog.Tokens |
KW_small | Language.Verilog.Tokens |
KW_solve | Language.Verilog.Tokens |
KW_specify | Language.Verilog.Tokens |
KW_specparam | Language.Verilog.Tokens |
KW_static | Language.Verilog.Tokens |
KW_strength0 | Language.Verilog.Tokens |
KW_strength1 | Language.Verilog.Tokens |
KW_string | Language.Verilog.Tokens |
KW_strong0 | Language.Verilog.Tokens |
KW_strong1 | Language.Verilog.Tokens |
KW_struct | Language.Verilog.Tokens |
KW_super | Language.Verilog.Tokens |
KW_supply0 | Language.Verilog.Tokens |
KW_supply1 | Language.Verilog.Tokens |
KW_table | Language.Verilog.Tokens |
KW_tagged | Language.Verilog.Tokens |
KW_task | Language.Verilog.Tokens |
KW_this | Language.Verilog.Tokens |
KW_throughout | Language.Verilog.Tokens |
KW_time | Language.Verilog.Tokens |
KW_timeprecision | Language.Verilog.Tokens |
KW_timeunit | Language.Verilog.Tokens |
KW_tran | Language.Verilog.Tokens |
KW_tranif0 | Language.Verilog.Tokens |
KW_tranif1 | Language.Verilog.Tokens |
KW_tri | Language.Verilog.Tokens |
KW_tri0 | Language.Verilog.Tokens |
KW_tri1 | Language.Verilog.Tokens |
KW_triand | Language.Verilog.Tokens |
KW_trior | Language.Verilog.Tokens |
KW_trireg | Language.Verilog.Tokens |
KW_type | Language.Verilog.Tokens |
KW_typedef | Language.Verilog.Tokens |
KW_type_option | Language.Verilog.Tokens |
KW_union | Language.Verilog.Tokens |
KW_unique | Language.Verilog.Tokens |
KW_unsigned | Language.Verilog.Tokens |
KW_use | Language.Verilog.Tokens |
KW_var | Language.Verilog.Tokens |
KW_vectored | Language.Verilog.Tokens |
KW_virtual | Language.Verilog.Tokens |
KW_void | Language.Verilog.Tokens |
KW_wait | Language.Verilog.Tokens |
KW_wait_order | Language.Verilog.Tokens |
KW_wand | Language.Verilog.Tokens |
KW_weak0 | Language.Verilog.Tokens |
KW_weak1 | Language.Verilog.Tokens |
KW_while | Language.Verilog.Tokens |
KW_wildcard | Language.Verilog.Tokens |
KW_wire | Language.Verilog.Tokens |
KW_with | Language.Verilog.Tokens |
KW_within | Language.Verilog.Tokens |
KW_wor | Language.Verilog.Tokens |
KW_xnor | Language.Verilog.Tokens |
KW_xor | Language.Verilog.Tokens |
Le | Language.Verilog.Types, Language.Verilog |
LHS | |
1 (Type/Class) | Language.Verilog.Types, Language.Verilog |
2 (Data Constructor) | Language.Verilog.Types, Language.Verilog |
LHSBit | Language.Verilog.Types, Language.Verilog |
LHSRange | Language.Verilog.Types, Language.Verilog |
Lit_number | Language.Verilog.Tokens |
Lit_number_unsigned | Language.Verilog.Tokens |
Lit_string | Language.Verilog.Tokens |
Lt | Language.Verilog.Types, Language.Verilog |
Mod | Language.Verilog.Types, Language.Verilog |
Module | |
1 (Type/Class) | Language.Verilog.Types, Language.Verilog |
2 (Data Constructor) | Language.Verilog.Types, Language.Verilog |
ModuleItem | Language.Verilog.Types, Language.Verilog |
Mul | Language.Verilog.Types, Language.Verilog |
Mux | Language.Verilog.Types, Language.Verilog |
Ne | Language.Verilog.Types, Language.Verilog |
NonBlockingAssignment | Language.Verilog.Types, Language.Verilog |
Not | Language.Verilog.Types, Language.Verilog |
Null | Language.Verilog.Types, Language.Verilog |
Number | Language.Verilog.Types, Language.Verilog |
Or | Language.Verilog.Types, Language.Verilog |
Output | Language.Verilog.Types, Language.Verilog |
Paremeter | Language.Verilog.Types, Language.Verilog |
parseFile | Language.Verilog.Parse, Language.Verilog |
Position | |
1 (Type/Class) | Language.Verilog.Tokens |
2 (Data Constructor) | Language.Verilog.Tokens |
preprocess | Language.Verilog.Preprocess |
Range | Language.Verilog.Types, Language.Verilog |
Reg | Language.Verilog.Types, Language.Verilog |
Repeat | Language.Verilog.Types, Language.Verilog |
Sense | |
1 (Type/Class) | Language.Verilog.Types, Language.Verilog |
2 (Data Constructor) | Language.Verilog.Types, Language.Verilog |
SenseNegedge | Language.Verilog.Types, Language.Verilog |
SenseOr | Language.Verilog.Types, Language.Verilog |
SensePosedge | Language.Verilog.Types, Language.Verilog |
ShiftL | Language.Verilog.Types, Language.Verilog |
ShiftR | Language.Verilog.Types, Language.Verilog |
Stmt | Language.Verilog.Types, Language.Verilog |
StmtCall | Language.Verilog.Types, Language.Verilog |
String | Language.Verilog.Types, Language.Verilog |
Sub | Language.Verilog.Types, Language.Verilog |
Sym_amp | Language.Verilog.Tokens |
Sym_amp_amp | Language.Verilog.Tokens |
Sym_amp_amp_amp | Language.Verilog.Tokens |
Sym_amp_eq | Language.Verilog.Tokens |
Sym_aster | Language.Verilog.Tokens |
Sym_aster_aster | Language.Verilog.Tokens |
Sym_aster_eq | Language.Verilog.Tokens |
Sym_aster_gt | Language.Verilog.Tokens |
Sym_aster_paren_r | Language.Verilog.Tokens |
Sym_at | Language.Verilog.Tokens |
Sym_at_aster | Language.Verilog.Tokens |
Sym_at_at_paren_l | Language.Verilog.Tokens |
Sym_bang | Language.Verilog.Tokens |
Sym_bang_eq | Language.Verilog.Tokens |
Sym_bang_eq_eq | Language.Verilog.Tokens |
Sym_bang_question_eq | Language.Verilog.Tokens |
Sym_bar | Language.Verilog.Tokens |
Sym_bar_bar | Language.Verilog.Tokens |
Sym_bar_dash_gt | Language.Verilog.Tokens |
Sym_bar_eq | Language.Verilog.Tokens |
Sym_bar_eq_gt | Language.Verilog.Tokens |
Sym_brace_l | Language.Verilog.Tokens |
Sym_brace_r | Language.Verilog.Tokens |
Sym_brack_l | Language.Verilog.Tokens |
Sym_brack_l_aster | Language.Verilog.Tokens |
Sym_brack_l_dash_gt | Language.Verilog.Tokens |
Sym_brack_l_eq | Language.Verilog.Tokens |
Sym_brack_r | Language.Verilog.Tokens |
Sym_colon | Language.Verilog.Tokens |
Sym_colon_colon | Language.Verilog.Tokens |
Sym_colon_eq | Language.Verilog.Tokens |
Sym_colon_slash | Language.Verilog.Tokens |
Sym_comma | Language.Verilog.Tokens |
Sym_dash | Language.Verilog.Tokens |
Sym_dash_colon | Language.Verilog.Tokens |
Sym_dash_dash | Language.Verilog.Tokens |
Sym_dash_eq | Language.Verilog.Tokens |
Sym_dash_gt | Language.Verilog.Tokens |
Sym_dash_gt_gt | Language.Verilog.Tokens |
Sym_dollar | Language.Verilog.Tokens |
Sym_dot | Language.Verilog.Tokens |
Sym_dot_aster | Language.Verilog.Tokens |
Sym_eq | Language.Verilog.Tokens |
Sym_eq_eq | Language.Verilog.Tokens |
Sym_eq_eq_eq | Language.Verilog.Tokens |
Sym_eq_gt | Language.Verilog.Tokens |
Sym_eq_question_eq | Language.Verilog.Tokens |
Sym_gt | Language.Verilog.Tokens |
Sym_gt_eq | Language.Verilog.Tokens |
Sym_gt_gt | Language.Verilog.Tokens |
Sym_gt_gt_eq | Language.Verilog.Tokens |
Sym_gt_gt_gt | Language.Verilog.Tokens |
Sym_gt_gt_gt_eq | Language.Verilog.Tokens |
Sym_hat | Language.Verilog.Tokens |
Sym_hat_eq | Language.Verilog.Tokens |
Sym_hat_tildy | Language.Verilog.Tokens |
Sym_lt | Language.Verilog.Tokens |
Sym_lt_eq | Language.Verilog.Tokens |
Sym_lt_lt | Language.Verilog.Tokens |
Sym_lt_lt_eq | Language.Verilog.Tokens |
Sym_lt_lt_lt | Language.Verilog.Tokens |
Sym_lt_lt_lt_eq | Language.Verilog.Tokens |
Sym_paren_l | Language.Verilog.Tokens |
Sym_paren_l_aster | Language.Verilog.Tokens |
Sym_paren_l_aster_paren_r | Language.Verilog.Tokens |
Sym_paren_r | Language.Verilog.Tokens |
Sym_percent | Language.Verilog.Tokens |
Sym_percent_eq | Language.Verilog.Tokens |
Sym_plus | Language.Verilog.Tokens |
Sym_plus_colon | Language.Verilog.Tokens |
Sym_plus_eq | Language.Verilog.Tokens |
Sym_plus_plus | Language.Verilog.Tokens |
Sym_pound | Language.Verilog.Tokens |
Sym_pound_pound | Language.Verilog.Tokens |
Sym_question | Language.Verilog.Tokens |
Sym_semi | Language.Verilog.Tokens |
Sym_slash | Language.Verilog.Tokens |
Sym_slash_eq | Language.Verilog.Tokens |
Sym_s_quote | Language.Verilog.Tokens |
Sym_tildy | Language.Verilog.Tokens |
Sym_tildy_amp | Language.Verilog.Tokens |
Sym_tildy_bar | Language.Verilog.Tokens |
Sym_tildy_hat | Language.Verilog.Tokens |
Token | |
1 (Type/Class) | Language.Verilog.Tokens |
2 (Data Constructor) | Language.Verilog.Tokens |
TokenInfo | Language.Verilog.Tokens |
tokenString | Language.Verilog.Tokens |
uncomment | Language.Verilog.Preprocess |
Unknown | Language.Verilog.Tokens |
Wire | Language.Verilog.Types, Language.Verilog |