Verismith.Verilog.Mutate

Functions to mutate the Verilog AST from Verismith.Verilog.AST to generate more random patterns, such as nesting wires instead of creating new ones.

Documentation

class Mutate a where

Methods

mutExpr :: (Expr -> Expr) -> a -> a

Instances

Mutate SourceInfo

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> SourceInfo -> SourceInfo

Mutate Verilog

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> Verilog -> Verilog

Mutate ModDecl

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> ModDecl -> ModDecl

Mutate ModItem

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> ModItem -> ModItem

Mutate LocalParam

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> LocalParam -> LocalParam

Mutate Parameter

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> Parameter -> Parameter

Mutate Statement

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> Statement -> Statement

Mutate ContAssign

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> ContAssign -> ContAssign

Mutate Assign

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> Assign -> Assign

Mutate ModConn

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> ModConn -> ModConn

Mutate Port

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> Port -> Port

Mutate Range

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> Range -> Range

Mutate PortType

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> PortType -> PortType

Mutate PortDir

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> PortDir -> PortDir

Mutate LVal

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> LVal -> LVal

Mutate Task

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> Task -> Task

Mutate ConstExpr

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> ConstExpr -> ConstExpr

Mutate Expr

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> Expr -> Expr

Mutate UnaryOperator

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> UnaryOperator -> UnaryOperator

Mutate BinaryOperator

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> BinaryOperator -> BinaryOperator

Mutate Event

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> Event -> Event

Mutate Delay

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> Delay -> Delay

Mutate Identifier

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> Identifier -> Identifier

Mutate a => Mutate [a]

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> [a] -> [a]

Mutate a => Mutate (Maybe a)

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> Maybe a -> Maybe a

Mutate a => Mutate (GenVerilog a)

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> GenVerilog a -> GenVerilog a

inPort :: Identifier -> ModDecl -> Bool

Return if the Identifier is in a ModDecl.

findAssign :: Identifier -> [ModItem] -> Maybe Expr

Find the last assignment of a specific wire/reg to an expression, and returns that expression.

idTrans :: Identifier -> Expr -> Expr -> Expr

Transforms an expression by replacing an Identifier with an expression. This is used inside transformOf and traverseExpr to replace the Identifier recursively.

replace :: Identifier -> Expr -> Expr -> Expr

Replaces the identifier recursively in an expression.

nestId :: Identifier -> ModDecl -> ModDecl

Nest expressions for a specific Identifier. If the Identifier is not found, the AST is not changed.

This could be improved by instead of only using the last assignment to the wire that one finds, to use the assignment to the wire before the current expression. This would require a different approach though.

nestSource :: Identifier -> Verilog -> Verilog

Replaces an identifier by a expression in all the module declaration.

nestUpTo :: Int -> Verilog -> Verilog

Nest variables in the format w[0-9]* up to a certain number.

allVars :: ModDecl -> [Identifier]

instantiateMod :: ModDecl -> ModDecl -> ModDecl

Add a Module Instantiation using ModInst from the first module passed to it to the body of the second module. It first has to make all the inputs into reg.

>>> render $ instantiateMod m main
module main;
  wire [(3'h4):(1'h0)] y;
  reg [(3'h4):(1'h0)] x;
  m m1(y, x);
endmodule

instantiateMod_ :: ModDecl -> ModItem

Instantiate without adding wire declarations. It also does not count the current instantiations of the same module.

>>> GenVerilog $ instantiateMod_ m
m m(y, x);

instantiateModSpec_ :: Text -> ModDecl -> ModItem

Instantiate without adding wire declarations. It also does not count the current instantiations of the same module.

>>> GenVerilog $ instantiateModSpec_ "_" m
m m(.y(y), .x(x));

filterChar :: Text -> [Identifier] -> [Identifier]

initMod :: ModDecl -> ModDecl

Initialise all the inputs and outputs to a module.

>>> GenVerilog $ initMod m
module m(y, x);
  output wire [(3'h4):(1'h0)] y;
  input wire [(3'h4):(1'h0)] x;
endmodule

makeIdFrom :: Show a => a -> Identifier -> Identifier

Make an Identifier from and existing Identifier and an object with a Show instance to make it unique.

makeTop :: Int -> ModDecl -> ModDecl

Make top level module for equivalence verification. Also takes in how many modules to instantiate.

makeTopAssert :: ModDecl -> ModDecl

Make a top module with an assert that requires y_1 to always be equal to y_2, which can then be proven using a formal verification tool.

simplify :: Expr -> Expr

Simplify an Expr by using constants to remove BinaryOperator and simplify expressions. To make this work effectively, it should be run until no more changes were made to the expression.

>>> GenVerilog . simplify $ (Id "x") + 0
x

>>> GenVerilog . simplify $ (Id "y") + (Id "x")
(y + x)

removeId :: [Identifier] -> Expr -> Expr

Remove all Identifier that do not appeare in the input list from an Expr. The identifier will be replaced by 1'b0, which can then later be simplified further.

>>> GenVerilog . removeId ["x"] $ Id "x" + Id "y"
(x + (1'h0))

combineAssigns :: Port -> [ModItem] -> [ModItem]

combineAssigns_ :: Bool -> Port -> [Port] -> ModItem

declareMod :: [Port] -> ModDecl -> ModDecl

Provide declarations for all the ports that are passed to it. If they are registers, it should assign them to 0.

fromPort :: Port -> Identifier