Verismith

Documentation

defaultMain :: IO ()

Types

data Opts

Constructors

Fuzz

Fields

• fuzzOutput :: !Text
• configFile :: !(Maybe FilePath)
• forced :: !Bool
• keepAll :: !Bool
• num :: !Int

Generate

Fields

• mFileName :: !(Maybe FilePath)
• configFile :: !(Maybe FilePath)

Parse

Fields

• fileName :: !FilePath

Reduce

Fields

• fileName :: !FilePath
• top :: !Text
• reduceScript :: !(Maybe FilePath)
• synthesiserDesc :: ![SynthDescription]
• rerun :: Bool

ConfigOpt

Fields

• writeConfig :: !(Maybe FilePath)
• configFile :: !(Maybe FilePath)
• doRandomise :: !Bool

data SourceInfo

Constructors

SourceInfo

Fields

• _infoTop :: !Text
• _infoSrc :: !Verilog

Instances

Eq SourceInfo

Defined in Verismith.Verilog.AST

Methods

(==) :: SourceInfo -> SourceInfo -> Bool

(/=) :: SourceInfo -> SourceInfo -> Bool

Data SourceInfo

Defined in Verismith.Verilog.AST

Methods

gfoldl :: (forall d b. Data d => c (d -> b) -> d -> c b) -> (forall g. g -> c g) -> SourceInfo -> c SourceInfo

gunfold :: (forall b r. Data b => c (b -> r) -> c r) -> (forall r. r -> c r) -> Constr -> c SourceInfo

toConstr :: SourceInfo -> Constr

dataTypeOf :: SourceInfo -> DataType

dataCast1 :: Typeable t => (forall d. Data d => c (t d)) -> Maybe (c SourceInfo)

dataCast2 :: Typeable t => (forall d e. (Data d, Data e) => c (t d e)) -> Maybe (c SourceInfo)

gmapT :: (forall b. Data b => b -> b) -> SourceInfo -> SourceInfo

gmapQl :: (r -> r' -> r) -> r -> (forall d. Data d => d -> r') -> SourceInfo -> r

gmapQr :: (r' -> r -> r) -> r -> (forall d. Data d => d -> r') -> SourceInfo -> r

gmapQ :: (forall d. Data d => d -> u) -> SourceInfo -> [u]

gmapQi :: Int -> (forall d. Data d => d -> u) -> SourceInfo -> u

gmapM :: Monad m => (forall d. Data d => d -> m d) -> SourceInfo -> m SourceInfo

gmapMp :: MonadPlus m => (forall d. Data d => d -> m d) -> SourceInfo -> m SourceInfo

gmapMo :: MonadPlus m => (forall d. Data d => d -> m d) -> SourceInfo -> m SourceInfo

Ord SourceInfo

Defined in Verismith.Verilog.AST

Methods

compare :: SourceInfo -> SourceInfo -> Ordering

(<) :: SourceInfo -> SourceInfo -> Bool

(<=) :: SourceInfo -> SourceInfo -> Bool

(>) :: SourceInfo -> SourceInfo -> Bool

(>=) :: SourceInfo -> SourceInfo -> Bool

max :: SourceInfo -> SourceInfo -> SourceInfo

min :: SourceInfo -> SourceInfo -> SourceInfo

Show SourceInfo

Defined in Verismith.Verilog.AST

Methods

showsPrec :: Int -> SourceInfo -> ShowS

show :: SourceInfo -> String

showList :: [SourceInfo] -> ShowS

Generic SourceInfo

Defined in Verismith.Verilog.AST

Associated Types

type Rep SourceInfo :: Type -> Type

Methods

from :: SourceInfo -> Rep SourceInfo x

to :: Rep SourceInfo x -> SourceInfo

NFData SourceInfo

Defined in Verismith.Verilog.AST

Methods

rnf :: SourceInfo -> ()

Source SourceInfo

Defined in Verismith.Verilog.CodeGen

Methods

genSource :: SourceInfo -> Text

Mutate SourceInfo

Defined in Verismith.Verilog.Mutate

Methods

mutExpr :: (Expr -> Expr) -> SourceInfo -> SourceInfo

type Rep SourceInfo

Defined in Verismith.Verilog.AST

type Rep SourceInfo = D1 (MetaData "SourceInfo" "Verismith.Verilog.AST" "verismith-0.4.0.0-inplace" False) (C1 (MetaCons "SourceInfo" PrefixI True) (S1 (MetaSel (Just "_infoTop") SourceUnpack SourceStrict DecidedStrict) (Rec0 Text) :*: S1 (MetaSel (Just "_infoSrc") NoSourceUnpackedness SourceStrict DecidedStrict) (Rec0 Verilog)))

Run functions

runEquivalence

Arguments

:: Maybe Seed

-> Gen Verilog

Generator for the Verilog file.

-> Text

Name of the folder on each thread.

-> Text

Name of the general folder being used.

-> Bool

Keep flag.

-> Int

Used to track the recursion.

-> IO ()

Run a fuzz run and check if all of the simulators passed by checking if the generated Verilog files are equivalent.

runSimulation :: IO ()

Run a simulation on a random DAG or a random module.

runReduce :: SourceInfo -> IO SourceInfo

draw :: IO ()

Draw a randomly generated DAG to a dot file and compile it to a png so it can be seen.

Verilog generation functions

procedural :: Text -> Config -> Gen Verilog

Procedural generation method for random Verilog. Uses internal Reader and State to keep track of the current Verilog code structure.

proceduralIO :: Text -> Config -> IO Verilog

Samples the Gen directly to generate random Verilog using the Text as the name of the main module and the configuration Config to influence the generation.

proceduralSrc :: Text -> Config -> Gen SourceInfo

Given a Text and a Config will generate a SourceInfo which has the top module set to the right name.

proceduralSrcIO :: Text -> Config -> IO SourceInfo

Sampled and wrapped into a SourceInfo with the given top module name.

randomMod :: MonadGen m => Int -> Int -> m ModDecl

Extra modules

module Verismith.Verilog

module Verismith.Config

module Verismith.Circuit

module Verismith.Sim

module Verismith.Fuzz

module Verismith.Report