Hackage :: [Package]

clash-ghc: CAES Language for Synchronous Hardware

[ bsd2, hardware, library, program ] [ Propose Tags ]

Clash is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The Clash compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of Clash:

This package provides:

Prelude library: http://hackage.haskell.org/package/clash-prelude

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Versions [faq] 0.2.1, 0.2.2, 0.2.2.1, 0.2.2.2, 0.3, 0.3.0.1, 0.3.0.2, 0.3.0.3, 0.3.1, 0.3.2, 0.3.3, 0.4, 0.4.1, 0.5, 0.5.1, 0.5.2, 0.5.3, 0.5.4, 0.5.5, 0.5.6, 0.5.7, 0.5.8, 0.5.9, 0.5.10, 0.5.11, 0.5.12, 0.5.13, 0.5.14, 0.5.15, 0.6, 0.6.1, 0.6.2, 0.6.3, 0.6.4, 0.6.5, 0.6.6, 0.6.7, 0.6.8, 0.6.9, 0.6.10, 0.6.11, 0.6.12, 0.6.13, 0.6.14, 0.6.15, 0.6.16, 0.6.17, 0.6.18, 0.6.19, 0.6.20, 0.6.21, 0.6.22, 0.6.23, 0.6.24, 0.7, 0.7.0.1, 0.7.1, 0.7.2, 0.99, 0.99.1, 0.99.2, 0.99.3, 1.0.0, 1.0.1 (info)
Change log CHANGELOG.md
Dependencies array (>=0.4 && <0.6), base (>=4.10 && <5), bifunctors (>=4.1.1 && <6.0), bytestring (>=0.9 && <0.11), clash-ghc, clash-lib (==1.0.*), clash-prelude (==1.0.*), concurrent-supply (>=0.1.7 && <0.2), containers (>=0.5.4.0 && <0.7), deepseq (>=1.3.0.2 && <1.5), directory (>=1.2 && <1.4), filepath (>=1.3 && <1.5), ghc (>=8.2.0 && <8.9), ghc-boot (>=8.2.0 && <8.9), ghc-prim (>=0.3.1.0 && <0.6), ghc-typelits-extra (>=0.3.1 && <0.4), ghc-typelits-knownnat (>=0.6 && <0.8), ghc-typelits-natnormalise (>=0.6 && <0.8), ghci (>=8.2.0 && <8.9), hashable (>=1.1.2.3 && <1.4), haskeline (>=0.7.0.3 && <0.8), integer-gmp (>=1.0.1.0 && <2.0), lens (>=4.0.5 && <4.19), mtl (>=2.1.1 && <2.3), primitive (>=0.5.0.1 && <1.0), process (>=1.2 && <1.7), reflection (>=2.1.2 && <3.0), template-haskell (>=2.8.0.0 && <2.16), text (>=1.2.2 && <1.3), time (>=1.4.0.1 && <1.10), transformers (>=0.5.2.0 && <0.6), uniplate (>=1.6.12 && <1.8), unix (>=2.7.1 && <2.9), unordered-containers (>=0.2.1.0 && <0.3), utf8-string (>=1.0.0.0 && <1.1.0.0), vector (>=0.11 && <1.0), Win32 (>=2.3.1 && <2.9) [details]
License BSD-2-Clause
Copyright Copyright © 2012-2016, University of Twente, 2016-2017, Myrtle Software Ltd, 2017-2019, QBayLogic B.V., Google Inc.
Author The Clash Authors
Maintainer QBayLogic B.V. <devops@qbaylogic.com>
Category Hardware
Home page http://www.clash-lang.org/
Bug tracker http://github.com/clash-lang/clash-compiler/issues
Source repo head: git clone https://github.com/clash-lang/clash-compiler.git
Uploaded by QBayLogic at Thu Oct 17 10:19:32 UTC 2019
Distributions NixOS:1.0.1
Executables clashi, clash
Downloads 39469 total (1768 in the last 30 days)
Rating 2.25 (votes: 2) [estimated by Bayesian average]
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Modules

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Flags

NameDescriptionDefaultType
dynamic

Build Clash binaries with GHC flag -dynamic. This flag should only be used for packaging purposes. Installations using cabal should use --enable-executable-dynamic!

DisabledManual
use-ghc-paths

Locate the GHC core libraries using the ghc-paths package. Note: this flag may make binaries less relocatable, by hard-coding an absolute path to the core libraries.

DisabledManual

Use -f <flag> to enable a flag, or -f -<flag> to disable that flag. More info

Downloads

Maintainer's Corner

For package maintainers and hackage trustees

Readme for clash-ghc-1.0.1

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clash-ghc - Haskell/GHC front-end for the Clash compiler

  • See the LICENSE file for license and copyright details
  • Contains code from the GHC compiler, see the LICENSE_GHC file for license and copyright details pertaining to that code.

Clash - A functional hardware description language

Clash is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The Clash compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of Clash:

  • Strongly typed (like VHDL), yet with a very high degree of type inference, enabling both safe and fast prototying using consise descriptions (like Verilog).

  • Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.

  • Higher-order functions, with type inference, result in designs that are fully parametric by default.

  • Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.

  • Support for multiple clock domains, with type safe clock domain crossing.

Support

For updates and questions join the mailing list clash-language+subscribe@googlegroups.com or read the forum